1. EE141 © Digital Integrated Circuits 2nd Timing Issues 1 Digital Integrated Circuits A Design Perspective Timing Issues Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić Revised from Digital Integrated Circuits, © Jan M. Rabaey el

2. EE141 © Digital Integrated Circuits 2nd Timing Issues 2 Digital Timing  All sequential circuits must have a well-defined ordering of the switching events to ensure the correct operation.  The very popular synchronous approach, in which all memory elements in the system are simultaneously updated using a globally distributed periodic synchronization signal, is an effective way to enforce correct ordering  But global synchronous clock might suffer from clock skew (spatial variation) and clock jitter (temporal variation)  Asynchronous design avoids the problem of clock uncertainty by eliminating the need for a globally distributed clock at expense of hardware and speed (not necessarily)

3. EE141 © Digital Integrated Circuits 2nd Timing Issues 3 Synchronous Timing

4. EE141 © Digital Integrated Circuits 2nd Timing Issues 4 Timing Definitions

5. EE141 © Digital Integrated Circuits 2nd Timing Issues 5 Latch Parameters D Clk Q D Q t c-q t hold PW m t su t d-q Delays can be different for rising and falling data transitions T

6. EE141 © Digital Integrated Circuits 2nd Timing Issues 6 Register Parameters D Clk Q D Q t c-q t hold T t su Delays can be different for rising and falling data transitions

7. EE141 © Digital Integrated Circuits 2nd Timing Issues 7 Clock Uncertainties Sources of clock uncertainty

8. EE141 © Digital Integrated Circuits 2nd Timing Issues 8 Clock Non-idealities  Clock skew  The spatial variation in arrival time of a clock transition on an integrated circuit is commonly referred to as clock skew  Clock skew is caused by static mismatches in the clock paths and differences in the clock load.  Clock skew is constant from cycle to cycle.  Clock skew does not cause clock period variation, but only phase shift  deterministic + random, t SK

9. EE141 © Digital Integrated Circuits 2nd Timing Issues 9 Clock Nonidealities  Clock jitter  Clock jitter refers to the temporal variation of the clock period at a given spatial location on the chip: the clock period can reduce or expand from cycle to cycle  Jitter can be measured and characterized in a number of ways and is typically modeled as a zero-mean random variable

10. EE141 © Digital Integrated Circuits 2nd Timing Issues 10 Clock Skew and Jitter Clk1 Clk2 t SK t JS

11. EE141 © Digital Integrated Circuits 2nd Timing Issues 11 Clock Skew # of registers Clk delay Insertion delay Max Clk skew Earliest occurrence of Clk edge Nominal –  /2 Latest occurrence of Clk edge Nominal +  /2  Clock skew might have strong effect for both the system performances and the functionality of sequential system

12. EE141 © Digital Integrated Circuits 2nd Timing Issues 12 Positive and Negative Skew

13. EE141 © Digital Integrated Circuits 2nd Timing Issues 13 Positive Skew Minimum cycle time: T +  >=t c-q + t su + t logic This means that clock skew has the potential to improve the performance of the circuit (minimum required clock period reduces!). However, increasing clock skew makes the circuit more susceptible to race conditions. To avoid race: t h +  <t c-q,cd + t logic,cd

14. EE141 © Digital Integrated Circuits 2nd Timing Issues 14 Negative Skew Receiving edge arrives before the launching edge On one hand, negative skew adversely impacts the performance (increase the clock period). On the other hand, negative skew implies that the system never fails (since receiving edge happens before)

15. EE141 © Digital Integrated Circuits 2nd Timing Issues 15 Summary for clock skew: minimum clock period Minimum cycle time: T +  = t c-q + t su + t logic Worst case is when receiving edge arrives early (negative  ) Cd: contamination delay or minimum delay

16. EE141 © Digital Integrated Circuits 2nd Timing Issues 16 Hold time constraint: t (c-q, cd) + t (logic, cd) > t hold +  Worst case is when receiving edge arrives late Race between data and clock Summary for clock skew: hold time constraint

17. EE141 © Digital Integrated Circuits 2nd Timing Issues 17 Impact of Jitter Clock period constraint: T-2t jitter >=t c-q + t logic + t setup

18. EE141 © Digital Integrated Circuits 2nd Timing Issues 18 Impact of clock jitter: general case Clk T T SU T Clk-Q T LM Latest point of launching Earliest arrival of next cycle T JI T c-q + T LM + T SU < T – T JI,1 – T JI,2

19. EE141 © Digital Integrated Circuits 2nd Timing Issues 19 Combined impact of clock skew and clock jitter: minimum clock period If launching edge is early and receiving edge is late, the data will not be too late if: T c-q + T LM + T SU < T – T JI,1 – T JI,2 +  T c-q + T LM + T SU -  + 2 T JI < T Skew can be either positive and negative But the equation shows that positive skew can provide a performance advantage On the other hand, clock jitter always have a negative impact on the minimum clock period

20. EE141 © Digital Integrated Circuits 2nd Timing Issues 20 Combined effect of clock Skew and Jitter Clk t SK t JS

21. EE141 © Digital Integrated Circuits 2nd Timing Issues 21 Earliest point of launching Combined impact of clock skew and clock jitter: minimum logic delay Clk T Clk-Q T Lm Data must not arrive before this time Clk THTH Nominal clock edge jitter skew

22. EE141 © Digital Integrated Circuits 2nd Timing Issues 22 Minimum logic delay: If launching edge is early and receiving edge is late: T c-q + T LM – T JI,1 < T + T JI,2 +  T c-q + T LM > T H + 2T JI +  Combined impact of clock skew and clock jitter: minimum logic delay As before, negative skew increase the clock period, but made minimum logic delay constraint easier to met On the other hand, clock jitter always have a negative impact on the minimum logic delay

23. EE141 © Digital Integrated Circuits 2nd Timing Issues 23 How to counter Clock Skew?

24. EE141 © Digital Integrated Circuits 2nd Timing Issues 24 Clock Distribution Techniques  Clock skew and jitter affects the system performance, so it is important to design a clock network to minimize both.  When designing clock network, power consumption is a big issue. In today’s digital processors, a majority of the power is dissipated in the clock network.  To reduce power consumption, part of the clock network should conditionally shut down  Clock network design is a complicated task with many degrees of freedom, such as material used for wires, basic topology and hierarchy, sizing of wires and buffers, rise time and fall time, load capacitance etc.

25. EE141 © Digital Integrated Circuits 2nd Timing Issues 25 Clock Distribution Techniques Clock is distributed in a tree-like fashion Balance path Approach: H-tree The absolute delay from a central clock source to the clock elements is irrelevant, only the relative phase or delay between any two clock elements is important.

26. EE141 © Digital Integrated Circuits 2nd Timing Issues 26 More realistic H-tree  The H-tree configuration is particularly useful for regular array networks in which all elements are identical and the clock can be distributed as a binary tree.  A more general approach, referred to as matched RC trees, represents a floorplan that distributes the clock signal so that the interconnections carrying the clock signals to the functional sub-blocks have equal time constants. (that is the general approach does not rely on a regular physical structure)

27. EE141 © Digital Integrated Circuits 2nd Timing Issues 27 More realistic H-tree [Restle98] An RC-matched IBM microprocessor 10 balanced load segments CLK

28. EE141 © Digital Integrated Circuits 2nd Timing Issues 28 The Grid System No rc-matching Rather, absolute delay is minimized Allows for late design changes Large power due to lengthy interconnect Grids are typically used in the final stage of a clock network to distribute the clock to the clocking elements.