6Clock Non-idealities Clock skew Clock jitter Spatial variation in temporally equivalent clock edges; deterministic + random, tSKClock jitterTemporal variations in consecutive edges of the clock signal; modulation + random noiseCycle-to-cycle (short-term) tJSLong term tJLVariation of the pulse widthImportant for level sensitive clocking
7Clock Skew and JitterClktSKClktJSBoth skew and jitter affect the effective cycle timeOnly skew affects the race margin
19Self-timed and Asynchronous Design Functions of clock in synchronous design1) Acts as completion signal2) Ensures the correct ordering of eventsTruly asynchronous design1) Completion is ensured by careful timing analysis2) Ordering of events is implicit in logicSelf-timed design1) Completion ensured by completion signal2) Ordering imposed by handshaking protocol
29Synchronizers and Arbiters Arbiter: Circuit to decide which of 2 events occurred firstSynchronizer: Arbiter with clock f as one of the inputsProblem: Circuit HAS to make a decision in limited time - which decision is not important
30A Simple Synchronizer • Data sampled on rising edge of the clock • Latch will eventually resolve the signal value,but ... this might take infinite time!