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EE141 © Digital Integrated Circuits 2nd Timing Issues 1 Digital Integrated Circuits A Design Perspective Timing Issues.

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Presentation on theme: "EE141 © Digital Integrated Circuits 2nd Timing Issues 1 Digital Integrated Circuits A Design Perspective Timing Issues."— Presentation transcript:

1 EE141 © Digital Integrated Circuits 2nd Timing Issues 1 Digital Integrated Circuits A Design Perspective Timing Issues

2 EE141 © Digital Integrated Circuits 2nd Timing Issues 2 Timing Definitions

3 EE141 © Digital Integrated Circuits 2nd Timing Issues 3 Latch Parameters D Clk Q D Q t c-q t hold PW m t su t d-q Delays can be different for rising and falling data transitions T

4 EE141 © Digital Integrated Circuits 2nd Timing Issues 4 Register Parameters D Clk Q D Q t c-q t hold T t su Delays can be different for rising and falling data transitions

5 EE141 © Digital Integrated Circuits 2nd Timing Issues 5 Clock Uncertainties Sources of clock uncertainty

6 EE141 © Digital Integrated Circuits 2nd Timing Issues 6 Clock Non-idealities  Clock skew  Spatial variation in temporally equivalent clock edges; deterministic + random, t SK  Clock jitter  Temporal variations in consecutive edges of the clock signal; modulation + random noise  Cycle-to-cycle (short-term) t JS  Long term t JL  Variation of the pulse width  Important for level sensitive clocking

7 EE141 © Digital Integrated Circuits 2nd Timing Issues 7 Clock Skew and Jitter  Both skew and jitter affect the effective cycle time  Only skew affects the race margin Clk t SK t JS

8 EE141 © Digital Integrated Circuits 2nd Timing Issues 8 Positive and Negative Skew

9 EE141 © Digital Integrated Circuits 2nd Timing Issues 9 Positive Skew Launching edge arrives before the receiving edge

10 EE141 © Digital Integrated Circuits 2nd Timing Issues 10 Negative Skew Receiving edge arrives before the launching edge

11 EE141 © Digital Integrated Circuits 2nd Timing Issues 11 Timing Constraints Minimum cycle time: T -  = t c-q + t su + t logic Worst case is when receiving edge arrives early (positive  )

12 EE141 © Digital Integrated Circuits 2nd Timing Issues 12 Impact of Jitter

13 EE141 © Digital Integrated Circuits 2nd Timing Issues 13 Longest Logic Path in Edge-Triggered Systems Clk T T SU T Clk-Q T LM Latest point of launching Earliest arrival of next cycle T JI + 

14 EE141 © Digital Integrated Circuits 2nd Timing Issues 14 Shortest Path Clk T Clk-Q T Lm Earliest point of launching Data must not arrive before this time Clk THTH Nominal clock edge

15 EE141 © Digital Integrated Circuits 2nd Timing Issues 15 Clock Skew

16 EE141 © Digital Integrated Circuits 2nd Timing Issues 16 Clock Distribution Clock is distributed in a tree-like fashion H-tree

17 EE141 © Digital Integrated Circuits 2nd Timing Issues 17 More realistic H-tree [Restle98]

18 EE141 © Digital Integrated Circuits 2nd Timing Issues 18 The Grid System No rc-matching Large power

19 EE141 © Digital Integrated Circuits 2nd Timing Issues 19 Self-timed and Asynchronous Design Functions of clock in synchronous design 1) Acts as completion signal 2) Ensures the correct ordering of events Truly asynchronous design 2) Ordering of events is implicit in logic 1) Completion is ensured by careful timing analysis Self-timed design 1) Completion ensured by completion signal 2) Ordering imposed by handshaking protocol

20 EE141 © Digital Integrated Circuits 2nd Timing Issues 20 Synchronous Pipelined Datapath

21 EE141 © Digital Integrated Circuits 2nd Timing Issues 21 Self-Timed Pipelined Datapath

22 EE141 © Digital Integrated Circuits 2nd Timing Issues 22 Completion Signal Generation

23 EE141 © Digital Integrated Circuits 2nd Timing Issues 23 Completion Signal Using Current Sensing

24 EE141 © Digital Integrated Circuits 2nd Timing Issues 24 Hand-Shaking Protocol Two Phase Handshake

25 EE141 © Digital Integrated Circuits 2nd Timing Issues 25 2-Phase Handshake Protocol Advantage : FAST - minimal # of signaling events (important for global interconnect) Disadvantage : edge - sensitive, has state

26 EE141 © Digital Integrated Circuits 2nd Timing Issues 26 4-Phase Handshake Protocol Slower, but unambiguous Also known as RTZ

27 EE141 © Digital Integrated Circuits 2nd Timing Issues 27 4-Phase Handshake Protocol Implementation using Muller-C elements

28 EE141 © Digital Integrated Circuits 2nd Timing Issues 28 Asynchronous-Synchronous Interface

29 EE141 © Digital Integrated Circuits 2nd Timing Issues 29 Synchronizers and Arbiters  Arbiter: Circuit to decide which of 2 events occurred first  Synchronizer: Arbiter with clock  as one of the inputs  Problem: Circuit HAS to make a decision in limited time - which decision is not important

30 EE141 © Digital Integrated Circuits 2nd Timing Issues 30 A Simple Synchronizer Data sampled on rising edge of the clock Latch will eventually resolve the signal value, but... this might take infinite time!

31 EE141 © Digital Integrated Circuits 2nd Timing Issues 31 Arbiters

32 EE141 © Digital Integrated Circuits 2nd Timing Issues 32 PLL-Based Synchronization

33 EE141 © Digital Integrated Circuits 2nd Timing Issues 33 PLL Block Diagram

34 EE141 © Digital Integrated Circuits 2nd Timing Issues 34 Phase Detector Output before filtering Transfer characteristic

35 EE141 © Digital Integrated Circuits 2nd Timing Issues 35 Phase-Frequency Detector

36 EE141 © Digital Integrated Circuits 2nd Timing Issues 36 PFD Response to Frequency

37 EE141 © Digital Integrated Circuits 2nd Timing Issues 37 Charge Pump

38 EE141 © Digital Integrated Circuits 2nd Timing Issues 38 Clock Generation using DLLs Phase Det Charge Pump Filter DL PDCPVCO ÷N÷N Delay-Locked Loop (Delay Line Based) Phase-Locked Loop (VCO-Based) U D U D f REF fOfO fOfO Filter

39 EE141 © Digital Integrated Circuits 2nd Timing Issues 39 Delay Locked Loop

40 EE141 © Digital Integrated Circuits 2nd Timing Issues 40 DLL-Based Clock Distribution

41 EE141 © Digital Integrated Circuits 2nd Timing Issues 41 Digital Integrated Circuits A Design Perspective Arithmetic Circuits

42 EE141 © Digital Integrated Circuits 2nd Timing Issues 42 A Generic Digital Processor

43 EE141 © Digital Integrated Circuits 2nd Timing Issues 43 Building Blocks for Digital Architectures Arithmetic unit - Bit-sliced datapath(adder, multiplier, shifter, comparator, etc.) Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, random logic.) - Counters Interconnect - Switches - Arbiters - Bus

44 EE141 © Digital Integrated Circuits 2nd Timing Issues 44 Bit-Sliced Design

45 EE141 © Digital Integrated Circuits 2nd Timing Issues 45 Bit-Sliced Datapath

46 EE141 © Digital Integrated Circuits 2nd Timing Issues 46 Itanium Integer Datapath Fetzer, Orton, ISSCC’02

47 EE141 © Digital Integrated Circuits 2nd Timing Issues 47 Adders

48 EE141 © Digital Integrated Circuits 2nd Timing Issues 48 Full-Adder

49 EE141 © Digital Integrated Circuits 2nd Timing Issues 49 The Binary Adder

50 EE141 © Digital Integrated Circuits 2nd Timing Issues 50 The Ripple-Carry Adder Worst case delay linear with the number of bits Goal: Make the fastest possible carry path circuit t d = O(N) t adder = (N-1)t carry + t sum

51 EE141 © Digital Integrated Circuits 2nd Timing Issues 51 Complimentary Static CMOS Full Adder 28 Transistors

52 EE141 © Digital Integrated Circuits 2nd Timing Issues 52 Inversion Property

53 EE141 © Digital Integrated Circuits 2nd Timing Issues 53 Minimize Critical Path by Reducing Inverting Stages Exploit Inversion Property

54 EE141 © Digital Integrated Circuits 2nd Timing Issues 54 Transmission Gate Full Adder

55 EE141 © Digital Integrated Circuits 2nd Timing Issues 55 Carry-Bypass Adder Also called Carry-Skip

56 EE141 © Digital Integrated Circuits 2nd Timing Issues 56 Carry-Bypass Adder (cont.) t adder = t setup + M tcarry + (N/M-1)t bypass + (M-1)t carry + t sum

57 EE141 © Digital Integrated Circuits 2nd Timing Issues 57 Carry Ripple versus Carry Bypass

58 EE141 © Digital Integrated Circuits 2nd Timing Issues 58 Carry-Select Adder

59 EE141 © Digital Integrated Circuits 2nd Timing Issues 59 Carry Select Adder: Critical Path

60 EE141 © Digital Integrated Circuits 2nd Timing Issues 60 Linear Carry Select

61 EE141 © Digital Integrated Circuits 2nd Timing Issues 61 Square Root Carry Select

62 EE141 © Digital Integrated Circuits 2nd Timing Issues 62 Adder Delays - Comparison

63 EE141 © Digital Integrated Circuits 2nd Timing Issues 63 LookAhead - Basic Idea

64 EE141 © Digital Integrated Circuits 2nd Timing Issues 64 Carry Lookahead Trees Can continue building the tree hierarchically.

65 EE141 © Digital Integrated Circuits 2nd Timing Issues 65 Tree Adders 16-bit radix-2 Kogge-Stone tree

66 EE141 © Digital Integrated Circuits 2nd Timing Issues 66 Tree Adders 16-bit radix-4 Kogge-Stone Tree

67 EE141 © Digital Integrated Circuits 2nd Timing Issues 67 Multipliers

68 EE141 © Digital Integrated Circuits 2nd Timing Issues 68 The Binary Multiplication

69 EE141 © Digital Integrated Circuits 2nd Timing Issues 69 The Array Multiplier

70 EE141 © Digital Integrated Circuits 2nd Timing Issues 70 The MxN Array Multiplier — Critical Path Critical Path 1 & 2

71 EE141 © Digital Integrated Circuits 2nd Timing Issues 71 Carry-Save Multiplier

72 EE141 © Digital Integrated Circuits 2nd Timing Issues 72 Wallace-Tree Multiplier

73 EE141 © Digital Integrated Circuits 2nd Timing Issues 73 Wallace-Tree Multiplier

74 EE141 © Digital Integrated Circuits 2nd Timing Issues 74 Multipliers —Summary

75 EE141 © Digital Integrated Circuits 2nd Timing Issues 75 Shifters

76 EE141 © Digital Integrated Circuits 2nd Timing Issues 76 The Binary Shifter

77 EE141 © Digital Integrated Circuits 2nd Timing Issues 77 The Barrel Shifter Area Dominated by Wiring

78 EE141 © Digital Integrated Circuits 2nd Timing Issues 78 4x4 barrel shifter Width barrel ~ 2 p m M


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