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Published byAnnabella Nesbit Modified over 2 years ago

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**Digital Integrated Circuits A Design Perspective**

EE141 Digital Integrated Circuits A Design Perspective Timing Issues

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Timing Definitions

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**Latch Parameters D Q Clk T Clk PWm tsu D thold tc-q td-q Q**

Delays can be different for rising and falling data transitions

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**Register Parameters D Q Clk T Clk thold D tsu tc-q Q**

Delays can be different for rising and falling data transitions

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Clock Uncertainties Sources of clock uncertainty

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**Clock Non-idealities Clock skew Clock jitter**

Spatial variation in temporally equivalent clock edges; deterministic + random, tSK Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) tJS Long term tJL Variation of the pulse width Important for level sensitive clocking

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Clock Skew and Jitter Clk tSK Clk tJS Both skew and jitter affect the effective cycle time Only skew affects the race margin

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**Positive and Negative Skew**

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Positive Skew Launching edge arrives before the receiving edge

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Negative Skew Receiving edge arrives before the launching edge

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**Timing Constraints Minimum cycle time: T - = tc-q + tsu + tlogic**

Worst case is when receiving edge arrives early (positive )

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Impact of Jitter

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**Longest Logic Path in Edge-Triggered Systems**

TJI + d TSU Clk TClk-Q TLM T Latest point of launching Earliest arrival of next cycle

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**Shortest Path Clk TClk-Q TLm Clk TH Earliest point of launching**

Data must not arrive before this time Nominal clock edge

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Clock Skew

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Clock Distribution H-tree Clock is distributed in a tree-like fashion

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More realistic H-tree [Restle98]

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The Grid System No rc-matching Large power

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**Self-timed and Asynchronous Design**

Functions of clock in synchronous design 1) Acts as completion signal 2) Ensures the correct ordering of events Truly asynchronous design 1) Completion is ensured by careful timing analysis 2) Ordering of events is implicit in logic Self-timed design 1) Completion ensured by completion signal 2) Ordering imposed by handshaking protocol

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**Synchronous Pipelined Datapath**

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**Self-Timed Pipelined Datapath**

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**Completion Signal Generation**

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**Completion Signal Using Current Sensing**

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**Hand-Shaking Protocol**

Two Phase Handshake

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**2-Phase Handshake Protocol**

Advantage : FAST - minimal # of signaling events (important for global interconnect) Disadvantage : edge - sensitive, has state

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**4-Phase Handshake Protocol**

Also known as RTZ Slower, but unambiguous

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**4-Phase Handshake Protocol**

Implementation using Muller-C elements

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**Asynchronous-Synchronous Interface**

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**Synchronizers and Arbiters**

Arbiter: Circuit to decide which of 2 events occurred first Synchronizer: Arbiter with clock f as one of the inputs Problem: Circuit HAS to make a decision in limited time - which decision is not important

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**A Simple Synchronizer • Data sampled on rising edge of the clock**

• Latch will eventually resolve the signal value, but ... this might take infinite time!

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Arbiters

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**PLL-Based Synchronization**

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PLL Block Diagram

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Phase Detector Output before filtering Transfer characteristic

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**Phase-Frequency Detector**

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**PFD Response to Frequency**

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Charge Pump

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**Clock Generation using DLLs**

Delay-Locked Loop (Delay Line Based) fREF U Phase Det Charge Pump DL D Filter fO Phase-Locked Loop (VCO-Based) fREF U PD CP VCO D ÷N Filter fO

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Delay Locked Loop

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**DLL-Based Clock Distribution**

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**Digital Integrated Circuits A Design Perspective**

EE141 Digital Integrated Circuits A Design Perspective Arithmetic Circuits

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**A Generic Digital Processor**

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**Building Blocks for Digital Architectures**

Arithmetic unit - Bit-sliced datapath (adder, multiplier, shifter, comparator, etc.) Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, random logic.) - Counters Interconnect - Switches - Arbiters - Bus

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Bit-Sliced Design

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Bit-Sliced Datapath

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**Itanium Integer Datapath**

Fetzer, Orton, ISSCC’02

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Adders

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Full-Adder

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The Binary Adder

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**The Ripple-Carry Adder**

Worst case delay linear with the number of bits td = O(N) tadder = (N-1)tcarry + tsum Goal: Make the fastest possible carry path circuit

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**Complimentary Static CMOS Full Adder**

28 Transistors

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Inversion Property

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**Minimize Critical Path by Reducing Inverting Stages**

Exploit Inversion Property

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**Transmission Gate Full Adder**

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Carry-Bypass Adder Also called Carry-Skip

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**Carry-Bypass Adder (cont.)**

tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum

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**Carry Ripple versus Carry Bypass**

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Carry-Select Adder

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**Carry Select Adder: Critical Path**

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Linear Carry Select

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**Square Root Carry Select**

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**Adder Delays - Comparison**

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LookAhead - Basic Idea

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Carry Lookahead Trees Can continue building the tree hierarchically.

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Tree Adders 16-bit radix-2 Kogge-Stone tree

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Tree Adders 16-bit radix-4 Kogge-Stone Tree

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Multipliers

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**The Binary Multiplication**

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The Array Multiplier

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**The MxN Array Multiplier — Critical Path**

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**Carry-Save Multiplier**

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**Wallace-Tree Multiplier**

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**Wallace-Tree Multiplier**

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Multipliers —Summary

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Shifters

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The Binary Shifter

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The Barrel Shifter Area Dominated by Wiring

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4x4 barrel shifter Widthbarrel ~ 2 pm M

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