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Digital Integrated Circuits A Design Perspective

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Presentation on theme: "Digital Integrated Circuits A Design Perspective"— Presentation transcript:

1 Digital Integrated Circuits A Design Perspective
EE141 Digital Integrated Circuits A Design Perspective Timing Issues

2 Timing Definitions

3 Latch Parameters D Q Clk T Clk PWm tsu D thold tc-q td-q Q
Delays can be different for rising and falling data transitions

4 Register Parameters D Q Clk T Clk thold D tsu tc-q Q
Delays can be different for rising and falling data transitions

5 Clock Uncertainties Sources of clock uncertainty

6 Clock Non-idealities Clock skew Clock jitter
Spatial variation in temporally equivalent clock edges; deterministic + random, tSK Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) tJS Long term tJL Variation of the pulse width Important for level sensitive clocking

7 Clock Skew and Jitter Clk tSK Clk tJS Both skew and jitter affect the effective cycle time Only skew affects the race margin

8 Positive and Negative Skew

9 Positive Skew Launching edge arrives before the receiving edge

10 Negative Skew Receiving edge arrives before the launching edge

11 Timing Constraints Minimum cycle time: T -  = tc-q + tsu + tlogic
Worst case is when receiving edge arrives early (positive )

12 Impact of Jitter

13 Longest Logic Path in Edge-Triggered Systems
TJI + d TSU Clk TClk-Q TLM T Latest point of launching Earliest arrival of next cycle

14 Shortest Path Clk TClk-Q TLm Clk TH Earliest point of launching
Data must not arrive before this time Nominal clock edge

15 Clock Skew

16 Clock Distribution H-tree Clock is distributed in a tree-like fashion

17 More realistic H-tree [Restle98]

18 The Grid System No rc-matching Large power

19 Self-timed and Asynchronous Design
Functions of clock in synchronous design 1) Acts as completion signal 2) Ensures the correct ordering of events Truly asynchronous design 1) Completion is ensured by careful timing analysis 2) Ordering of events is implicit in logic Self-timed design 1) Completion ensured by completion signal 2) Ordering imposed by handshaking protocol

20 Synchronous Pipelined Datapath

21 Self-Timed Pipelined Datapath

22 Completion Signal Generation

23 Completion Signal Using Current Sensing

24 Hand-Shaking Protocol
Two Phase Handshake

25 2-Phase Handshake Protocol
Advantage : FAST - minimal # of signaling events (important for global interconnect) Disadvantage : edge - sensitive, has state

26 4-Phase Handshake Protocol
Also known as RTZ Slower, but unambiguous

27 4-Phase Handshake Protocol
Implementation using Muller-C elements

28 Asynchronous-Synchronous Interface

29 Synchronizers and Arbiters
Arbiter: Circuit to decide which of 2 events occurred first Synchronizer: Arbiter with clock f as one of the inputs Problem: Circuit HAS to make a decision in limited time - which decision is not important

30 A Simple Synchronizer • Data sampled on rising edge of the clock
• Latch will eventually resolve the signal value, but ... this might take infinite time!

31 Arbiters

32 PLL-Based Synchronization

33 PLL Block Diagram

34 Phase Detector Output before filtering Transfer characteristic

35 Phase-Frequency Detector

36 PFD Response to Frequency

37 Charge Pump

38 Clock Generation using DLLs
Delay-Locked Loop (Delay Line Based) fREF U Phase Det Charge Pump DL D Filter fO Phase-Locked Loop (VCO-Based) fREF U PD CP VCO D ÷N Filter fO

39 Delay Locked Loop

40 DLL-Based Clock Distribution

41 Digital Integrated Circuits A Design Perspective
EE141 Digital Integrated Circuits A Design Perspective Arithmetic Circuits

42 A Generic Digital Processor

43 Building Blocks for Digital Architectures
Arithmetic unit - Bit-sliced datapath (adder, multiplier, shifter, comparator, etc.) Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, random logic.) - Counters Interconnect - Switches - Arbiters - Bus

44 Bit-Sliced Design

45 Bit-Sliced Datapath

46 Itanium Integer Datapath
Fetzer, Orton, ISSCC’02

47 Adders

48 Full-Adder

49 The Binary Adder

50 The Ripple-Carry Adder
Worst case delay linear with the number of bits td = O(N) tadder = (N-1)tcarry + tsum Goal: Make the fastest possible carry path circuit

51 Complimentary Static CMOS Full Adder
28 Transistors

52 Inversion Property

53 Minimize Critical Path by Reducing Inverting Stages
Exploit Inversion Property

54 Transmission Gate Full Adder

55 Carry-Bypass Adder Also called Carry-Skip

56 Carry-Bypass Adder (cont.)
tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum

57 Carry Ripple versus Carry Bypass

58 Carry-Select Adder

59 Carry Select Adder: Critical Path

60 Linear Carry Select

61 Square Root Carry Select

62 Adder Delays - Comparison

63 LookAhead - Basic Idea

64 Carry Lookahead Trees Can continue building the tree hierarchically.

65 Tree Adders 16-bit radix-2 Kogge-Stone tree

66 Tree Adders 16-bit radix-4 Kogge-Stone Tree

67 Multipliers

68 The Binary Multiplication

69 The Array Multiplier

70 The MxN Array Multiplier — Critical Path

71 Carry-Save Multiplier

72 Wallace-Tree Multiplier

73 Wallace-Tree Multiplier

74 Multipliers —Summary

75 Shifters

76 The Binary Shifter

77 The Barrel Shifter Area Dominated by Wiring

78 4x4 barrel shifter Widthbarrel ~ 2 pm M

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