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**Digital Integrated Circuits A Design Perspective**

EE141 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić Timing Issues January 2003

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Synchronous Timing

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Timing Definitions

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**Latch Parameters D Q Clk T Clk PWm tsu D thold tc-q td-q Q**

Delays can be different for rising and falling data transitions

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**Register Parameters D Q Clk T Clk thold D tsu tc-q Q**

Delays can be different for rising and falling data transitions

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Clock Uncertainties Sources of clock uncertainty

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**Clock Nonidealities Clock skew Clock jitter**

Spatial variation in temporally equivalent clock edges; deterministic + random, tSK Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) tJS Long term tJL Variation of the pulse width Important for level sensitive clocking

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Clock Skew and Jitter Clk tSK Clk tJS Both skew and jitter affect the effective cycle time Only skew affects the race margin

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**Clock Skew # of registers Earliest occurrence of Clk edge**

Nominal – /2 Latest occurrence of Clk edge Nominal + /2 Clk delay Insertion delay Max Clk skew

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**Positive and Negative Skew**

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Positive Skew Launching edge arrives before the receiving edge

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Negative Skew Receiving edge arrives before the launching edge

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**Timing Constraints Minimum cycle time: T - = tc-q + tsu + tlogic**

Worst case is when receiving edge arrives early (positive )

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**Timing Constraints Hold time constraint:**

t(c-q, cd) + t(logic, cd) > thold + Worst case is when receiving edge arrives late Race between data and clock

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Impact of Jitter

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**Longest Logic Path in Edge-Triggered Systems**

TJI + d TSU Clk TClk-Q TLM T Latest point of launching Earliest arrival of next cycle

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**Clock Constraints in Edge-Triggered Systems**

If launching edge is late and receiving edge is early, the data will not be too late if: Tc-q + TLM + TSU < T – TJI,1 – TJI,2 - d Minimum cycle time is determined by the maximum delays through the logic Tc-q + TLM + TSU + d + 2 TJI < T Skew can be either positive or negative

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**Shortest Path Clk TClk-Q TLm Clk TH Earliest point of launching**

Data must not arrive before this time Nominal clock edge

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**Clock Constraints in Edge-Triggered Systems**

If launching edge is early and receiving edge is late: Tc-q + TLM – TJI,1 < TH + TJI,2 + d Minimum logic delay Tc-q + TLM < TH + 2TJI+ d

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**How to counter Clock Skew?**

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**Flip-Flop – Based Timing**

Skew Flip-flop delay Logic delay f TSU TClk-Q Flip -flop f = 1 f = 0 Logic Representation after M. Horowitz, VLSI Circuits 1996.

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**Flip-Flops and Dynamic Logic**

Logic delay TSU TSU TClk-Q TClk-Q f = 1 f = 1 f = 0 f = 0 Logic delay Precharge Precharge Evaluate Evaluate Flip-flops are used only with static logic

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**Latch timing tD-Q When data arrives to transparent latch**

Latch is a ‘soft’ barrier D Q Clk tClk-Q When data arrives to closed latch Data has to be ‘re-launched’

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**Single-Phase Clock with Latches**

f Latch Logic Tskl Tskl Tskt Tskt Clk PW P

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**Latch-Based Design L1 latch is transparent when f = 0**

Logic Latch Latch Logic

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Slack-borrowing

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**Latch-Based Timing f = 1 f = 0 Can tolerate skew! Skew Static logic**

L2 latch f = 1 L1 L2 Logic Latch Latch L1 latch Logic f = 0 Long path Can tolerate skew! Short path

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Clock Distribution H-tree Clock is distributed in a tree-like fashion

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More realistic H-tree [Restle98]

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The Grid System No rc-matching Large power

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Example: DEC Alpha 21164

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**21164 Clocking Clock waveform Location of clock driver on die**

EE141 21164 Clocking tcycle= 3.3ns 2 phase single wire clock, distributed globally 2 distributed driver channels Reduced RC delay/skew Improved thermal distribution 3.75nF clock load 58 cm final driver width Local inverters for latching Conditional clocks in caches to reduce power More complex race checking Device variation trise = 0.35ns tskew = 150ps Clock waveform pre-driver final drivers Location of clock driver on die

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**Clock Skew in Alpha Processor**

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**EV6 (Alpha 21264) Clocking 600 MHz – 0.35 micron CMOS trise = 0.35ns**

EE141 EV6 (Alpha 21264) Clocking 600 MHz – 0.35 micron CMOS trise = 0.35ns tskew = 50ps tcycle= 1.67ns Global clock waveform 2 Phase, with multiple conditional buffered clocks 2.8 nF clock load 40 cm final driver width Local clocks can be gated “off” to save power Reduced load/skew Reduced thermal issues Multiple clocks complicate race checking

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21264 Clocking

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**(20% to 80% Extrapolated to 0% to 100%)**

EE141 EV6 Clock Results ps 300 305 310 315 320 325 330 335 340 345 ps 5 10 15 20 25 30 35 40 45 50 GCLK Skew (at Vdd/2 Crossings) GCLK Rise Times (20% to 80% Extrapolated to 0% to 100%)

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**EV7 Clock Hierarchy Active Skew Management and Multiple Clock Domains**

EE141 EV7 Clock Hierarchy Active Skew Management and Multiple Clock Domains + widely dispersed drivers + DLLs compensate static and low- frequency variation + divides design and verification effort - DLL design and verification is added work + tailored clocks

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**Self-timed and Asynchronous Design**

Functions of clock in synchronous design 1) Acts as completion signal 2) Ensures the correct ordering of events Truly asynchronous design 1) Completion is ensured by careful timing analysis 2) Ordering of events is implicit in logic Self-timed design 1) Completion ensured by completion signal 2) Ordering imposed by handshaking protocol

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**Synchronous Pipelined Datapath**

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**Self-Timed Pipelined Datapath**

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**Completion Signal Generation**

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**Completion Signal Generation**

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**Completion Signal in DCVSL**

DD DD B Start Done B 1 B B 1 In 1 In 1 PDN PDN In 2 In 2 Start

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Self-Timed Adder

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**Completion Signal Using Current Sensing**

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**Hand-Shaking Protocol**

Two Phase Handshake

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**Event Logic – The Muller-C Element**

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**2-Phase Handshake Protocol**

Advantage : FAST - minimal # of signaling events (important for global interconnect) Disadvantage : edge - sensitive, has state

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**Example: Self-timed FIFO**

All 1s or 0s -> pipeline empty Alternating 1s and 0s -> pipeline full

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2-Phase Protocol

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Example From [Horowitz]

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Example

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Example

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Example

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**4-Phase Handshake Protocol**

Also known as RTZ Slower, but unambiguous

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**4-Phase Handshake Protocol**

Implementation using Muller-C elements

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Self-Resetting Logic Post-charge logic

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Clock-Delayed Domino

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**Asynchronous-Synchronous Interface**

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**Synchronizers and Arbiters**

Arbiter: Circuit to decide which of 2 events occurred first Synchronizer: Arbiter with clock f as one of the inputs Problem: Circuit HAS to make a decision in limited time - which decision is not important Caveat: It is impossible to ensure correct operation But, we can decrease the error probability at the expense of delay

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**A Simple Synchronizer • Data sampled on rising edge of the clock**

• Latch will eventually resolve the signal value, but ... this might take infinite time!

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**Synchronizer: Output Trajectories**

Single-pole model for a flip-flop

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Mean Time to Failure

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Example

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Influence of Noise Low amplitude noise does not influence synchronization behavior

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**Typical Synchronizers**

2 phase clocking circuit Using delay line

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**Cascaded Synchronizers Reduce MTF**

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Arbiters

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**PLL-Based Synchronization**

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PLL Block Diagram

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Phase Detector Output before filtering Transfer characteristic

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**Phase-Frequency Detector**

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**PFD Response to Frequency**

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**PFD Phase Transfer Characteristic**

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Charge Pump

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PLL Simulation

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**Clock Generation using DLLs**

Delay-Locked Loop (Delay Line Based) fREF U Phase Det Charge Pump DL D Filter fO Phase-Locked Loop (VCO-Based) fREF U PD CP VCO D ÷N Filter fO

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Delay Locked Loop

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**DLL-Based Clock Distribution**

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