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EE141 © Digital Integrated Circuits 2nd Timing Issues 1 Digital Integrated Circuits A Design Perspective Timing Issues Jan M. Rabaey Anantha Chandrakasan.

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Presentation on theme: "EE141 © Digital Integrated Circuits 2nd Timing Issues 1 Digital Integrated Circuits A Design Perspective Timing Issues Jan M. Rabaey Anantha Chandrakasan."— Presentation transcript:

1 EE141 © Digital Integrated Circuits 2nd Timing Issues 1 Digital Integrated Circuits A Design Perspective Timing Issues Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić January 2003

2 EE141 © Digital Integrated Circuits 2nd Timing Issues 2 Synchronous Timing

3 EE141 © Digital Integrated Circuits 2nd Timing Issues 3 Timing Definitions

4 EE141 © Digital Integrated Circuits 2nd Timing Issues 4 Latch Parameters D Clk Q D Q t c-q t hold PW m t su t d-q Delays can be different for rising and falling data transitions T

5 EE141 © Digital Integrated Circuits 2nd Timing Issues 5 Register Parameters D Clk Q D Q t c-q t hold T t su Delays can be different for rising and falling data transitions

6 EE141 © Digital Integrated Circuits 2nd Timing Issues 6 Clock Uncertainties Sources of clock uncertainty

7 EE141 © Digital Integrated Circuits 2nd Timing Issues 7 Clock Nonidealities  Clock skew  Spatial variation in temporally equivalent clock edges; deterministic + random, t SK  Clock jitter  Temporal variations in consecutive edges of the clock signal; modulation + random noise  Cycle-to-cycle (short-term) t JS  Long term t JL  Variation of the pulse width  Important for level sensitive clocking

8 EE141 © Digital Integrated Circuits 2nd Timing Issues 8 Clock Skew and Jitter  Both skew and jitter affect the effective cycle time  Only skew affects the race margin Clk t SK t JS

9 EE141 © Digital Integrated Circuits 2nd Timing Issues 9 Clock Skew # of registers Clk delay Insertion delay Max Clk skew Earliest occurrence of Clk edge Nominal –  /2 Latest occurrence of Clk edge Nominal +  /2 

10 EE141 © Digital Integrated Circuits 2nd Timing Issues 10 Positive and Negative Skew

11 EE141 © Digital Integrated Circuits 2nd Timing Issues 11 Positive Skew Launching edge arrives before the receiving edge

12 EE141 © Digital Integrated Circuits 2nd Timing Issues 12 Negative Skew Receiving edge arrives before the launching edge

13 EE141 © Digital Integrated Circuits 2nd Timing Issues 13 Timing Constraints Minimum cycle time: T -  = t c-q + t su + t logic Worst case is when receiving edge arrives early (positive  )

14 EE141 © Digital Integrated Circuits 2nd Timing Issues 14 Timing Constraints Hold time constraint: t (c-q, cd) + t (logic, cd) > t hold +  Worst case is when receiving edge arrives late Race between data and clock

15 EE141 © Digital Integrated Circuits 2nd Timing Issues 15 Impact of Jitter

16 EE141 © Digital Integrated Circuits 2nd Timing Issues 16 Longest Logic Path in Edge-Triggered Systems Clk T T SU T Clk-Q T LM Latest point of launching Earliest arrival of next cycle T JI + 

17 EE141 © Digital Integrated Circuits 2nd Timing Issues 17 Clock Constraints in Edge-Triggered Systems If launching edge is late and receiving edge is early, the data will not be too late if: Minimum cycle time is determined by the maximum delays through the logic T c-q + T LM + T SU < T – T JI,1 – T JI,2 -  T c-q + T LM + T SU +  + 2 T JI < T Skew can be either positive or negative

18 EE141 © Digital Integrated Circuits 2nd Timing Issues 18 Shortest Path Clk T Clk-Q T Lm Earliest point of launching Data must not arrive before this time Clk THTH Nominal clock edge

19 EE141 © Digital Integrated Circuits 2nd Timing Issues 19 Clock Constraints in Edge-Triggered Systems Minimum logic delay If launching edge is early and receiving edge is late: T c-q + T LM – T JI,1 < T H + T JI,2 +  T c-q + T LM < T H + 2T JI + 

20 EE141 © Digital Integrated Circuits 2nd Timing Issues 20 How to counter Clock Skew?

21 EE141 © Digital Integrated Circuits 2nd Timing Issues 21 Flip-Flop – Based Timing Flip -flop Logic    Flip-flop delay Skew Logic delay T SU T Clk-Q Representation after M. Horowitz, VLSI Circuits 1996.

22 EE141 © Digital Integrated Circuits 2nd Timing Issues 22 Flip-Flops and Dynamic Logic   Logic delay T SU T Clk-Q   Logic delay T SU T Clk-Q Precharge Evaluate Precharge Flip-flops are used only with static logic

23 EE141 © Digital Integrated Circuits 2nd Timing Issues 23 Latch timing D Clk Q t D-Q t Clk-Q When data arrives to transparent latch When data arrives to closed latch Data has to be ‘re-launched’ Latch is a ‘soft’ barrier

24 EE141 © Digital Integrated Circuits 2nd Timing Issues 24 Single-Phase Clock with Latches Latch Logic  Clk P PW T skl T skt

25 EE141 © Digital Integrated Circuits 2nd Timing Issues 25 Latch-Based Design L1 Latch Logic L2 Latch  L1 latch is transparent when  = 0 L2 latch is transparent when  = 1

26 EE141 © Digital Integrated Circuits 2nd Timing Issues 26 Slack-borrowing

27 EE141 © Digital Integrated Circuits 2nd Timing Issues 27 Latch-Based Timing L1 Latch Logic L2 Latch    L1 latch L2 latch Skew Can tolerate skew! Long path Short path Static logic

28 EE141 © Digital Integrated Circuits 2nd Timing Issues 28 Clock Distribution Clock is distributed in a tree-like fashion H-tree

29 EE141 © Digital Integrated Circuits 2nd Timing Issues 29 More realistic H-tree [Restle98]

30 EE141 © Digital Integrated Circuits 2nd Timing Issues 30 The Grid System No rc-matching Large power

31 EE141 © Digital Integrated Circuits 2nd Timing Issues 31 Example: DEC Alpha 21164

32 EE141 © Digital Integrated Circuits 2nd Timing Issues Clocking  2 phase single wire clock, distributed globally  2 distributed driver channels  Reduced RC delay/skew  Improved thermal distribution  3.75nF clock load  58 cm final driver width  Local inverters for latching  Conditional clocks in caches to reduce power  More complex race checking  Device variation t rise = 0.35ns t skew = 150ps t cycle = 3.3ns Clock waveform Location of clock driver on die pre-driver final drivers

33 EE141 © Digital Integrated Circuits 2nd Timing Issues 33

34 EE141 © Digital Integrated Circuits 2nd Timing Issues 34 Clock Skew in Alpha Processor

35 EE141 © Digital Integrated Circuits 2nd Timing Issues 35  2 Phase, with multiple conditional buffered clocks  2.8 nF clock load  40 cm final driver width  Local clocks can be gated “off” to save power  Reduced load/skew  Reduced thermal issues  Multiple clocks complicate race checking t rise = 0.35nst skew = 50ps t cycle = 1.67ns EV6 (Alpha 21264) Clocking 600 MHz – 0.35 micron CMOS Global clock waveform

36 EE141 © Digital Integrated Circuits 2nd Timing Issues Clocking

37 EE141 © Digital Integrated Circuits 2nd Timing Issues 37 EV6 Clock Results GCLK Skew (at Vdd/2 Crossings) ps ps GCLK Rise Times (20% to 80% Extrapolated to 0% to 100%)

38 EE141 © Digital Integrated Circuits 2nd Timing Issues 38 EV7 Clock Hierarchy + widely dispersed drivers + DLLs compensate static and low- frequency variation + divides design and verification effort - DLL design and verification is added work + tailored clocks Active Skew Management and Multiple Clock Domains

39 EE141 © Digital Integrated Circuits 2nd Timing Issues 39 Self-timed and Asynchronous Design Functions of clock in synchronous design 1) Acts as completion signal 2) Ensures the correct ordering of events Truly asynchronous design 2) Ordering of events is implicit in logic 1) Completion is ensured by careful timing analysis Self-timed design 1) Completion ensured by completion signal 2) Ordering imposed by handshaking protocol

40 EE141 © Digital Integrated Circuits 2nd Timing Issues 40 Synchronous Pipelined Datapath

41 EE141 © Digital Integrated Circuits 2nd Timing Issues 41 Self-Timed Pipelined Datapath

42 EE141 © Digital Integrated Circuits 2nd Timing Issues 42 Completion Signal Generation

43 EE141 © Digital Integrated Circuits 2nd Timing Issues 43 Completion Signal Generation

44 EE141 © Digital Integrated Circuits 2nd Timing Issues 44 Completion Signal in DCVSL PDN B0 In B1 Start V DD V Done B0 B1

45 EE141 © Digital Integrated Circuits 2nd Timing Issues 45 Self-Timed Adder

46 EE141 © Digital Integrated Circuits 2nd Timing Issues 46 Completion Signal Using Current Sensing

47 EE141 © Digital Integrated Circuits 2nd Timing Issues 47 Hand-Shaking Protocol Two Phase Handshake

48 EE141 © Digital Integrated Circuits 2nd Timing Issues 48 Event Logic – The Muller-C Element

49 EE141 © Digital Integrated Circuits 2nd Timing Issues 49 2-Phase Handshake Protocol Advantage : FAST - minimal # of signaling events (important for global interconnect) Disadvantage : edge - sensitive, has state

50 EE141 © Digital Integrated Circuits 2nd Timing Issues 50 Example: Self-timed FIFO All 1s or 0s -> pipeline empty Alternating 1s and 0s -> pipeline full

51 EE141 © Digital Integrated Circuits 2nd Timing Issues 51 2-Phase Protocol

52 EE141 © Digital Integrated Circuits 2nd Timing Issues 52 Example From [Horowitz]

53 EE141 © Digital Integrated Circuits 2nd Timing Issues 53 Example

54 EE141 © Digital Integrated Circuits 2nd Timing Issues 54 Example

55 EE141 © Digital Integrated Circuits 2nd Timing Issues 55 Example

56 EE141 © Digital Integrated Circuits 2nd Timing Issues 56 4-Phase Handshake Protocol Slower, but unambiguous Also known as RTZ

57 EE141 © Digital Integrated Circuits 2nd Timing Issues 57 4-Phase Handshake Protocol Implementation using Muller-C elements

58 EE141 © Digital Integrated Circuits 2nd Timing Issues 58 Self-Resetting Logic Post-charge logic

59 EE141 © Digital Integrated Circuits 2nd Timing Issues 59 Clock-Delayed Domino

60 EE141 © Digital Integrated Circuits 2nd Timing Issues 60 Asynchronous-Synchronous Interface

61 EE141 © Digital Integrated Circuits 2nd Timing Issues 61 Synchronizers and Arbiters  Arbiter: Circuit to decide which of 2 events occurred first  Synchronizer: Arbiter with clock  as one of the inputs  Problem: Circuit HAS to make a decision in limited time - which decision is not important  Caveat: It is impossible to ensure correct operation  But, we can decrease the error probability at the expense of delay

62 EE141 © Digital Integrated Circuits 2nd Timing Issues 62 A Simple Synchronizer Data sampled on rising edge of the clock Latch will eventually resolve the signal value, but... this might take infinite time!

63 EE141 © Digital Integrated Circuits 2nd Timing Issues 63 Synchronizer: Output Trajectories Single-pole model for a flip-flop

64 EE141 © Digital Integrated Circuits 2nd Timing Issues 64 Mean Time to Failure

65 EE141 © Digital Integrated Circuits 2nd Timing Issues 65 Example

66 EE141 © Digital Integrated Circuits 2nd Timing Issues 66 Influence of Noise Low amplitude noise does not influence synchronization behavior

67 EE141 © Digital Integrated Circuits 2nd Timing Issues 67 Typical Synchronizers Using delay line 2 phase clocking circuit

68 EE141 © Digital Integrated Circuits 2nd Timing Issues 68 Cascaded Synchronizers Reduce MTF

69 EE141 © Digital Integrated Circuits 2nd Timing Issues 69 Arbiters

70 EE141 © Digital Integrated Circuits 2nd Timing Issues 70 PLL-Based Synchronization

71 EE141 © Digital Integrated Circuits 2nd Timing Issues 71 PLL Block Diagram

72 EE141 © Digital Integrated Circuits 2nd Timing Issues 72 Phase Detector Output before filtering Transfer characteristic

73 EE141 © Digital Integrated Circuits 2nd Timing Issues 73 Phase-Frequency Detector

74 EE141 © Digital Integrated Circuits 2nd Timing Issues 74 PFD Response to Frequency

75 EE141 © Digital Integrated Circuits 2nd Timing Issues 75 PFD Phase Transfer Characteristic

76 EE141 © Digital Integrated Circuits 2nd Timing Issues 76 Charge Pump

77 EE141 © Digital Integrated Circuits 2nd Timing Issues 77 PLL Simulation

78 EE141 © Digital Integrated Circuits 2nd Timing Issues 78 Clock Generation using DLLs Phase Det Charge Pump Filter DL PDCPVCO ÷N÷N Delay-Locked Loop (Delay Line Based) Phase-Locked Loop (VCO-Based) U D U D f REF fOfO fOfO Filter

79 EE141 © Digital Integrated Circuits 2nd Timing Issues 79 Delay Locked Loop

80 EE141 © Digital Integrated Circuits 2nd Timing Issues 80 DLL-Based Clock Distribution


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