Presentation is loading. Please wait.

Presentation is loading. Please wait.

4/22/2015 1 Clock Network Synthesis Prof. Shiyan Hu Office: EREC 731.

Similar presentations


Presentation on theme: "4/22/2015 1 Clock Network Synthesis Prof. Shiyan Hu Office: EREC 731."— Presentation transcript:

1 4/22/ Clock Network Synthesis Prof. Shiyan Hu Office: EREC 731

2 2 4/22/2015 Outline Introduction H-tree Zero skew clock DME and its extension New trends

3 3 4/22/2015 Introduction For synchronized designs, data transfer between functional elements are synchronized by clock signals Clock signal are generated externally (e.g., by PLL) Clock period equation t d : Longest path through combinational logic t skew : Clock skew t su : Setup time of the synchronizing elements

4 4 4/22/2015 Clock Skew Clock skew is the maximum difference in the arrival time of a clock signal at two different components. Clock skew forces designers to use a large time period between clock pulses. This makes the system slower. So, in addition to other objectives, clock skew should be minimized during clock routing.

5 5 4/22/2015 Clock Design Problem What are the main concerns for clock design? Skew –No. 1 concern for clock networks –For increased clock frequency, skew may contribute over 10% of the system cycle time Power –very important, as clock is a major power consumer –It switches at every clock cycle Noise –Clock is often a very strong aggressor –May need shielding Delay –Not really important –But slew rate is important (sharp transition)

6 6 4/22/2015 The Clock Routing Problem Given a source and n sinks. Connect all sinks to the source by an interconnect tree so as to minimize: –Clock Skew = max i,j |t i - t j | –Delay = max i t i –Total wirelength –Noise and coupling effect

7 7 4/22/2015 Clock Design Considerations Clock signal is global in nature, so clock nets are usually very long. –Significant interconnect capacitance and resistance So what are the techniques? –Routing Clock tree versus clock clock mesh (grid) Balance skew and total wire length –Buffer insertion Clock buffers to reduce clock skew, delay, and distortion in waveform. –Wire sizing To further tune the clock tree/mesh

8 8 4/22/2015 Clock trees A path from the clock source to clock sinks Clock Source FF

9 9 4/22/2015 Clock trees A path from the clock source to clock sinks Clock Source FF

10 10 4/22/2015 H-tree Algorithm Minimize skew by making interconnections to subunits equal in length –Regular pattern Can be used when terminals are evenly distributed –However, this is never the case in practice –So strict (pure) H-trees are rarely used –However, still popular for top-level clock network design –Cons: too costly is used everywhere

11 11 4/22/2015

12 12 4/22/2015 A Zero Skew Algorithm Use Elmore delay model to compute delay Try to minimize wire length, but not done very well –Lots of follow up works to minimize total wire length while maintaining zero skew –DME and its extensions

13 13 4/22/2015 An Exact Zero Skew Algorithm [Tsay’93]

14 14 4/22/2015 A Zero Skew Algorithm [Tsay’91] This paper built the foundation for zero skew Its principal can also be used to do prescribed skew (just solve a slightly different delay equation with non- zero skew) However, its merging is kind of simple May have too much total wire length

15 15 4/22/2015 Deferred Merge Embedding As its name implies, DME defers the merging as late as possible, to make sure minimal wire length cost for merging Independently proposed by several groups –Edahiro, NEC Res Dev, 1991 –Chao et al, DAC’92 –Boese and Kahng, ASIC’92 DME needs an abstract routing topology as the input It has a bottom-up phase followed by a top-down process

16 16 4/22/2015 Bottom Up Phase Each node v has a merging segment ms(v). A merging segment is a Manhattan arc Manhattan arc: has slope +/- 1 or has zero length (could be a point). tiled rectangular region (TRR): The collection of points within a fixed distance from a Manhattan arc. The intersection of two TRR’s is a TRR Merging segments are always Manhattan arcs

17 17 4/22/2015

18 18 4/22/2015

19 19 4/22/2015 DME is guaranteed to find the minimum wire length with zero skew under the linear delay model Need to have an abstract routing graph to start with DME Wrapup [Boese and Kahng, ASIC’92]

20 20 4/22/2015 Modification: Bounded Skew Instead of choosing merging segments as in DME, choose merging region of v, mr(v) Maintains skew bound Use boundary merging and embedding which considers merging points lying on the nearest boundary segments of mr(a) and mr(b)

21 21 4/22/2015 Topology Generation One common approach –Balanced and geometry guided –Top down-partitioning that recursively divide the set of sinks, using alternating horizontal and vertical cuts –The balance bipartition heuristic generates a topology that recursively divides the set of sinks into two subsets with equal total loading capacitance Balanced tree versus unbalanced tree? Geometric versus capacitive load? –[Chaturvedi and Hu, ICCD’03] has good survey of recent works –Abstract topology not just geometric, but also capacitive load, with prescribed skew

22 22 4/22/2015 Trend Clock skew scheduling together with clock tree synthesis –Schedule the timing slack of a circuit to the individual registers for optimal performance and as a second criteria to increase the robustness of the implementation w.r.t. process variation. Variability is a major concern Non-tree clock, mixed mesh/tree? –How to analyze it? –The task is to investigate a combined optimization for clock skew scheduling and clock tree synthesis such that any unintentional clock skew is maximally compensated by a corresponding slack at the registers. (P. Restle)


Download ppt "4/22/2015 1 Clock Network Synthesis Prof. Shiyan Hu Office: EREC 731."

Similar presentations


Ads by Google