13 Adding Two Numbers Many Types of Adders: Some examples: Bit Serial AdderAdd time = n x fCascade StagesRipple carry adderAdd time = n x tPDCarry Look Ahead AdderGenerate carries in parallele.g., 4-bit AM Can have “look ahead” of the “look ahead” units.
15 Negative Numbers and Subtraction Several different codes for negative numbers2's complement1's complementsigned magnitudeothersFor 2's complement, subtraction is implemented with the same hardware by negating the subtrahend. This is done by inverting each bit and adding one. The one can be added by setting the carry-in to the first stage equal to 1, saving an operation.
24 Sequential LogicThe combinational logic circuits we have been studying so far have no memory. The outputs always follow the inputs.There is a need for circuits with a memory, which behave differently depending upon their previous state.Sequential circuits use current input variables and previous input variables by storing the information and putting back into the circuit on the next clock (activation) cycle.
27 The Clock Paces the System In a positive logic system, the “action”happens when the clock is high, or positive. The low part of the clock cycle allows propagation between subcircuits, so their inputs are stable at the correct value when the clock next goes high.
28 Clock Pulse Definition Positive PulsePositiveEdgeNegativeNegative PulsePositiveEdgeNegativeEdges can also be referred to as leading and trailing.
29 A NOR Gate with a Lumped Delay This delay between input and output is at the basis of the functioning of an important memory element, the flip-flop.
30 Flip-FlopsFlip-flops are the first stage in sequential logic design which incorporates memory (storage of previous states).
31 Types of Flip-Flops SR type Flip-flop or Set / Reset D type Flip-flop or Data / DelayJK type Flip-flopT type Flip-flop or Triggered /Toggle
32 The S-R (Set-Reset) Flip-Flop The operation of an SR flip-flop is as follows: The Set input will make Q goto 1The Reset input will make the output Q goto 0 i.e. reset the output. Both Set and Reset at logic 1 is not allowed as this is not a logical pair of inputs.The S-R flip-flop is an active high (positive logic) device.
33 A Clocked S-R Flip-Flop The clock signal, CLK, turns on the inputs to the flip-flop.
34 The Clocked D (Data) Flip-Flop The operation of the D type flip-flop is as follows: Any input appearing (present state) at the input D, will be produced at the output Q in time T+1 (next state).The operation of the D type delays any input by exactly one clock cycle.Cascading several D type flip-flops together can produce delaying circuitsThe clocked D flip-flop, sometimes called a latch, has a potential problem: If D changes while the clock is high, the output will also change. The Master-Slave flip-flop solves this problem:
35 8 Bits D (Data) Flip-Flop One D type flip-flop can store one bit of information for one clock cycle.To have eight bits of information, simply arrange eight flip-flops in parallel with a common clock.
36 The Master-Slave Flip-Flop The rising edge of the clock clocks new data into the Master, while the slave holds previous data. The falling edge clocks the new Master data into the Slave.