 EE2420 – Digital Logic Summer II 2013

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EE2420 – Digital Logic Summer II 2013
Set 13: Sequential Logic Class Book: Chapter 7 Online Book: Chapter 10 Hassan Salamy Ingram School of Engineering Texas State University

Combinatorial Logic Has a set output determined directly by the inputs
Used to implement direct digital logic functions Is described by a truth table describing their function

Combinatorial Circuit examples
Direct combinations of Logic Functions Adders Encoders and Decoders Multiplexers and Demultiplexers Parity Circuits Shifters

Storage elements Previously, we have considered combinational circuits where the output values depend only on the values of signals applied to the inputs Another class of logic circuits have the property that the outputs depend not only on the current inputs, but also on the past behavior of the circuit Such circuits include storage elements that store the values of logic signals

Sequential circuits Contents of the storage elements represent the state of the circuit Input value changes may leave the circuit in the same state or cause it to change to a new state Over time, the circuit changes through a sequence of states as a result of changes in the inputs Circuits that exhibit this behavior are referred to as sequential circuits

Sequential Logic Circuits
Latches Flip-flops Counters Registers Synchronous Sequential Logic Circuits

Alarm control system Set Sensor Memory element Alarm On/Off’ Reset
Suppose we wish to construct an alarm circuit such that the output remains active (on) even after the sensor output that triggered the alarm goes off A typical car alarm is representative of this type of circuit The circuit requires a memory element to remember that the alarm has to be active until a reset signal arrives Memory element Alarm Sensor Reset Set On/Off’

A simple memory element
B Simple memory element: feedback path provides basis for the ‘remembering’ of data. For the circuit above B=A’ and A=B’ This leads to two possible stable states: A=0 and B=1 A=1 and B=0 We cannot readily choose or change which state occurs. We need a way to select the stored state.

Basic SR latch Reset (R) Q Set (S)
A similar circuit, constructed with NOR gates can also be useful Inputs, Set and Reset, provide the means to changing the state, Q, of the circuit This circuit is referred to as a basic latch The output state of a latch is controlled by the state of its’ inputs Reset (R) Set (S) Q

Basic SR latch R Q a b S S R Qa Qb 0/1 1/0 (no change) 1
When R=S=0 the circuit remains in its current state (either Qa=1 and Qb=0 or Qa=0 and Qb=1) When S=1 and R=0, the latch is set into a state where Qa=1 and Qb=0 When S=0 and R=1, the latch is reset into a state where Qa=0 and Qb=1 Where S=1 and R=1, Qa=Qb=0 (there are actually problems with this state as we will see) S R Qa Qb 0/1 1/0 (no change) 1 Q a b R S

Basic SR latch timing diagram
Time 1 R S Q a b ? t 2 3 4 5 6 7 8 9 10

Basic SR latch timing diagram
If the propagation delays from Qa and Qb are exactly the same, the oscillation at time t10 would continue indefinitely In a real circuit there would probably be some (mostly insignificant) difference in the delays and the latch would eventually settle into one of its two stable states (but we don’t know which one it would be) Thus the S=R=1 combination is generally considered an unallowed combination in the SR latch

Gated SR latch The basic SR latch changes its state whenever its inputs change It may be desirable to add an enable signal to the basic SR latch that allows us to control when the circuit can change states Such a circuit is referred to as a gated SR latch

Gated SR latch circuit Q(t)=present state Q(t+1)=next state Q R * S
Clk CLK S R Q(t+1) X Q(t) 1 S R clk Q Q(t)=present state Q(t+1)=next state

Gated SR latch timing diagram
Clk Q S 1 ? Time

Gated SR latch with NAND gates
Clk Q

Gated D latch S D (Data) Q Clk R
Another useful latch has a single data input, D, and it stores the value of this input under the control of a clock signal This is referred to as a gated D latch Useful in circuits where we want to store some value The output of an adder/subtractor circuit would be one example S Q R Clk D (Data)

Gated D latch CLK D Q(t+1) X Q(t) 1 D clk Q Time t 1 2 3 4 Clk D Q

Level versus edge sensitivity
Since the output of the D latch is controlled by the level (0 or 1) of the clock input, the latch is said to be level sensitive All of the latches we have seen have been level sensitive It is possible to design a storage element for which the output only changes at the point in time when the clock changes from one value to another Such circuits are said to be edge triggered

Effects of propagation delays
Previously we have ignored the effects of propagation delay. In practical circuits, it is essential to account for these delays For the gated D latch (and others as well), it is important that the value of D not change at the time the clock (clk) goes from 1 to 0 The designer must make sure the signal is stable when the critical change in the clock takes place The minimum time the D signal must remain stable prior to the negative edge (1->0) of the clock signal is called the setup time (tsu) The minimum time the D signal must remain stable after the negative edge of clock is the hold time (th) Typical CMOS values are: tsu=3ns and th=2ns

Setup and hold times t su h Clk D Q

Flip-flops The gated latch circuits presented are level sensitive and can change states more than once during the ‘active’ period of the clock signal Circuits (storage elements) that can change their state no more than once during a clock period are also useful Two types of circuits with such behavior Master-slave flip-flip Edge-triggered flip-flop

Master-slave D flip-flop
Consists of 2 gated D latches The first, master, changes its state while clock=1 The second, slave, changes its state while clock=0 D Q Master Slave Clock m s Clk 38 transistors

Master-slave D flip-flop
When clock=1, the master tracks the values of the D input signal and the slave does not change Thus Qm follows any changes in D and Qs remains constant When the clock signal changes to 0, the master stage stops following the changes in the D input signal At the same time, the slave stage responds to the value of Qm and changes states accordingly Since Qm does not change when clock=0, the slave stage undergoes at most one change of state during a clock cycle From an output point of view, the circuit changes Qs (its output) at the negative edge of the clock signal

Master-slave D flip-flop
Clock Q m s = D clock Q

Edge-triggered flip-flop
A circuit, similar in functionality to the master-slave D flip-flop, can be constructed with 6 NAND gates D Clock P4 P3 P1 P2 5 6 1 2 3 Q 4 D clock Q Positive-edge-triggered D type flip-flop 24 transistors

Edge-triggered flip-flop
The previous circuit responds on the positive edge of the clock signal A negative-edge triggered D flip-flop can be constructed by replacing the NAND with NOR gates D clock Q D clock Q Positive-edge-triggered D type flip-flop Negative-edge-triggered D type flip-flop

Comparing D storage elements
Q clock clk Qb Qa Qc clock D Q a Q b Q c

Clear and preset inputs
It may be desirable to specifically set (Q=1) or clear (Q=0) a flip-flop Practical flip-flops often have preset and clear inputs Generally, these inputs are asynchronous (they do not depend on the clock signal) D clock Q Clear’ Preset’ As long as Preset’=0, Q=1 As long as Clear’=0, Q=0

T flip-flop Another flip-flop type, the T flip-flop, can be derived from the basic D flip-flop presented Feedback connections make the input signal D equal to the value of Q or Q’ under control of a signal labeled T D Q T Clock

T flip-flop The name T derives from the behavior of the circuit, which ‘toggles’ its state when T=1 This feature makes the T flip-flop a useful element when constructing counter circuits Clock T Q T Q(t+1) Q(t) 1 Q’(t) T clock Q Positive edge triggered

JK flip-flop The JK flip-flop can also be derived from the basic D flip-flop such that D=JQ’+K’Q The JK flip-flop combines aspects of the SR and the T flip-flop It behaves as the SR flip-flop (where J=S and K=R) for all values except J=K=1 For J=K=1, it toggles like the T flip-flop

JK flip-flop D Q J Clock K J clock Q K Positive edge triggered J K
Q(t+1) Q(t) 1 Q’(t) J clock Q K Positive edge triggered

JK flip-flop timing diagram
Complete the following timing diagram K Clk Q J 1 Time

Registers A flip-flop stores one bit of information
When a set of n flip-flops is used to store n bits of data, we refer to these flip-flops as a register Common register usages include Holding a data value output from an arithmetic circuit Holding a count value in a counter circuit A common clock signal is typically used for each flip-flop in a register

Shift register A register that provides the ability to shift its contents by a single bit May be to the right or left (or possibly both) Q Q Q Q 1 2 3 4 In D Q D Q D Q D Q Out Clock Q Q Q Q Shift right register

Shift right register Data is shifted to the right in a serial fashion using the In input Positive edge triggered Contents of each flip-flop are transferred to the next flip-flop at each positive edge of the clock Level sensitive devices would not be appropriate for this circuit In Q1 Q2 Q3 Q4 t0 1 t1 t2 t3 t4 t5 t6 t7

Parallel-access shift register
Data transfer in computer systems is a common function If the transfer is n-bits at a time, the transfer is said to be in parallel If the transfer is 1-bit at a time, the transfer is said to be serial To transfer data serially, data is loaded into a register in parallel (in one clock cycle) and then shifted out one bit at a time Parallel-to-serial data conversion If bits are received serially, after n clock cycles the contents of a register can be accessed in parallel as an n-bit item Serial-to-parallel conversion

Parallel-access shift register
Q 3 2 1 Clock Parallel input Parallel output Shift/Load Serial input D

Counters Special purpose arithmetic circuits used for the purpose of counting Design circuits that can increment or decrement a count by 1 Counter circuits serve many purposes Count occurrences of certain events Generate timing intervals for controlling various tasks in a digital system Track elapsed time between events Often (but not always) built with T flip-flops because the toggle feature is naturally suited for implementing the counting operation

Up-counter with T flip-flops
Q Clock 1 2 Clock Q 1 2 Count 3 4 5 6 7

Down counter with T flip-flops
Q Clock 1 2 Clock Q 1 2 Count 7 6 5 4 3

Asynchronous counters
The previous counters are examples of asynchronous counters. Also called ripple counters. Input clock is only connected to one flip-flop Clocks for other flip-flops are (or are derived from) the outputs of the previous flip-flops This form of counter is slow because the cascaded clocking scheme The clock source ripples from stage-to-stage The ripple effect is similar to that of a ripple carry adder circuit

Synchronous counters Q2 Q1 Q0 1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8 Synchronous counters are built by clocking all the flip-flops at the same time (with a single clocking source) Faster response than asynchronous counters Synchronous counters with T flip- flops Least significant bit, Q0, changes every clock cycle Bit one, Q1, only changes when Q0=1 Bit two, Q2, only changes when Q0=Q1=1 Q1 changes Q2 changes

T flip-flop synchronous counter
Q Clock 1 2 3 4-bit synchronous up counter

Enable and clear capability
It may be desirable to disable counting or clear the counter Include an enable control signal Use a flip-flop with asynchronous clear capability T Q Clock Enable Clear

D flip-flop synchronous counter
A 4-bit up counter counts in the sequence 0,1,2,…,15,0,1… The count is given by the flip-flop outputs Q3Q2Q1Q0 The D inputs are given by: D0=Q0ÅEnable D1=Q1ÅQ0×Enable D2= Q2ÅQ1×Q0×Enable D3= Q3ÅQ2×Q1×Q0×Enable

Four-bit counter (D flip-flops)
Clock Enable D Q Q0 Q1 Q2 Q3 Carry output