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EE2420 – Digital Logic Summer II 2013 Hassan Salamy Ingram School of Engineering Texas State University Set 13: Sequential Logic Class Book: Chapter 7.

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Presentation on theme: "EE2420 – Digital Logic Summer II 2013 Hassan Salamy Ingram School of Engineering Texas State University Set 13: Sequential Logic Class Book: Chapter 7."— Presentation transcript:

1 EE2420 – Digital Logic Summer II 2013 Hassan Salamy Ingram School of Engineering Texas State University Set 13: Sequential Logic Class Book: Chapter 7 Online Book: Chapter 10

2 Combinatorial Logic  Has a set output determined directly by the inputs  Used to implement direct digital logic functions  Is described by a truth table describing their function 2

3 Combinatorial Circuit examples  Direct combinations of Logic Functions  Adders  Encoders and Decoders  Multiplexers and Demultiplexers  Parity Circuits  Shifters 3

4 Storage elements  Previously, we have considered combinational circuits where the output values depend only on the values of signals applied to the inputs  Another class of logic circuits have the property that the outputs depend not only on the current inputs, but also on the past behavior of the circuit  Such circuits include storage elements that store the values of logic signals 4

5 Sequential circuits  Contents of the storage elements represent the state of the circuit  Input value changes may leave the circuit in the same state or cause it to change to a new state  Over time, the circuit changes through a sequence of states as a result of changes in the inputs  Circuits that exhibit this behavior are referred to as sequential circuits 5

6 Sequential Logic Circuits  Latches  Flip-flops  Counters  Registers  Synchronous Sequential Logic Circuits 6

7 Alarm control system  Suppose we wish to construct an alarm circuit such that the output remains active (on) even after the sensor output that triggered the alarm goes off  A typical car alarm is representative of this type of circuit  The circuit requires a memory element to remember that the alarm has to be active until a reset signal arrives Memory element Alarm Sensor Reset Set On/Off’ 7

8 A simple memory element  For the circuit above B=A’ and A=B’  This leads to two possible stable states: 1. A=0 and B=1 2. A=1 and B=0  We cannot readily choose or change which state occurs.  We need a way to select the stored state. AB Simple memory element: feedback path provides basis for the ‘remembering’ of data. 8

9 Basic SR latch  A similar circuit, constructed with NOR gates can also be useful  Inputs, Set and Reset, provide the means to changing the state, Q, of the circuit  This circuit is referred to as a basic latch  The output state of a latch is controlled by the state of its’ inputs Reset (R) Set (S) Q 9

10 Basic SR latch  When R=S=0 the circuit remains in its current state (either Q a =1 and Q b =0 or Q a =0 and Q b =1)  When S=1 and R=0, the latch is set into a state where Q a =1 and Q b =0  When S=0 and R=1, the latch is reset into a state where Q a =0 and Q b =1  Where S=1 and R=1, Q a =Q b =0 (there are actually problems with this state as we will see) Q a Q b R S SRQaQa QbQb 000/11/0(no change)

11 Basic SR latch timing diagram Time R S Q a Q b ? ? t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 11

12 Basic SR latch timing diagram  If the propagation delays from Q a and Q b are exactly the same, the oscillation at time t 10 would continue indefinitely  In a real circuit there would probably be some (mostly insignificant) difference in the delays and the latch would eventually settle into one of its two stable states (but we don’t know which one it would be)  Thus the S=R=1 combination is generally considered an unallowed combination in the SR latch 12

13 Gated SR latch  The basic SR latch changes its state whenever its inputs change  It may be desirable to add an enable signal to the basic SR latch that allows us to control when the circuit can change states  Such a circuit is referred to as a gated SR latch 13

14 Gated SR latch circuit Q Q R * S * R S Clk CLKSRQ(t+1) 0XXQ(t) X Q(t)=present state Q(t+1)=next state S R clk Q Q 14

15 Gated SR latch timing diagram R Clk Q Q S ? ? Time 15

16 Gated SR latch with NAND gates S R Clk Q Q 16

17 Gated D latch  Another useful latch has a single data input, D, and it stores the value of this input under the control of a clock signal  This is referred to as a gated D latch  Useful in circuits where we want to store some value  The output of an adder/subtractor circuit would be one example S Q R Clk D (Data) Q 17

18 Gated D latch Time t 1 t 2 t 3 t 4 Clk D Q CLKDQ(t+1) 0XQ(t) D clk Q Q 18

19 Level versus edge sensitivity  Since the output of the D latch is controlled by the level (0 or 1) of the clock input, the latch is said to be level sensitive  All of the latches we have seen have been level sensitive  It is possible to design a storage element for which the output only changes at the point in time when the clock changes from one value to another  Such circuits are said to be edge triggered 19

20 Effects of propagation delays  Previously we have ignored the effects of propagation delay. In practical circuits, it is essential to account for these delays  For the gated D latch (and others as well), it is important that the value of D not change at the time the clock (clk) goes from 1 to 0  The designer must make sure the signal is stable when the critical change in the clock takes place  The minimum time the D signal must remain stable prior to the negative edge (1->0) of the clock signal is called the setup time (t su )  The minimum time the D signal must remain stable after the negative edge of clock is the hold time (t h )  Typical CMOS values are: t su =3ns and t h =2ns 20

21 Setup and hold times t su t h Clk D Q 21

22 Flip-flops  The gated latch circuits presented are level sensitive and can change states more than once during the ‘active’ period of the clock signal  Circuits (storage elements) that can change their state no more than once during a clock period are also useful  Two types of circuits with such behavior  Master-slave flip-flip  Edge-triggered flip-flop 22

23 Master-slave D flip-flop  Consists of 2 gated D latches  The first, master, changes its state while clock=1  The second, slave, changes its state while clock=0 D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s Clk 38 transistors 23

24 Master-slave D flip-flop  When clock=1, the master tracks the values of the D input signal and the slave does not change  Thus Q m follows any changes in D and Q s remains constant  When the clock signal changes to 0, the master stage stops following the changes in the D input signal  At the same time, the slave stage responds to the value of Q m and changes states accordingly  Since Q m does not change when clock=0, the slave stage undergoes at most one change of state during a clock cycle  From an output point of view, the circuit changes Q s (its output) at the negative edge of the clock signal 24

25 Master-slave D flip-flop D Clock Q m QQ s = D clock Q Q 25

26 Edge-triggered flip-flop  A circuit, similar in functionality to the master-slave D flip-flop, can be constructed with 6 NAND gates D Clock P4 P3 P1 P Q Q 4 24 transistors D clock Q Q Positive-edge-triggered D type flip-flop 26

27 Edge-triggered flip-flop  The previous circuit responds on the positive edge of the clock signal  A negative-edge triggered D flip-flop can be constructed by replacing the NAND with NOR gates D clock Q Q Positive-edge-triggered D type flip-flop Negative-edge-triggered D type flip-flop D clock Q Q 27

28 Comparing D storage elements D Q Q D clock Q Q D clk Q Q D QbQb QaQa QcQc D clock Q a Q b Q c 28

29 Clear and preset inputs  It may be desirable to specifically set (Q=1) or clear (Q=0) a flip-flop  Practical flip-flops often have preset and clear inputs  Generally, these inputs are asynchronous (they do not depend on the clock signal) D clock Q Q Clear’ Preset’ As long as Preset’=0, Q=1 As long as Clear’=0, Q=0 29

30 T flip-flop  Another flip-flop type, the T flip-flop, can be derived from the basic D flip-flop presented  Feedback connections make the input signal D equal to the value of Q or Q’ under control of a signal labeled T D Q Q Q Q T Clock 30

31 T flip-flop  The name T derives from the behavior of the circuit, which ‘toggles’ its state when T=1  This feature makes the T flip-flop a useful element when constructing counter circuits TQ(t+1) 0Q(t) 1Q’(t) T clock Q Q Clock T Q Positive edge triggered 31

32 JK flip-flop  The JK flip-flop can also be derived from the basic D flip-flop such that D=JQ’+K’Q  The JK flip-flop combines aspects of the SR and the T flip-flop  It behaves as the SR flip-flop (where J=S and K=R) for all values except J=K=1  For J=K=1, it toggles like the T flip-flop 32

33 JK flip-flop D Q Q Q Q J Clock K JKQ(t+1) 00Q(t) Q’(t) J clock Q Q K Positive edge triggered 33

34 JK flip-flop timing diagram K Clk Q Q J Time Complete the following timing diagram 34

35 Registers  A flip-flop stores one bit of information  When a set of n flip-flops is used to store n bits of data, we refer to these flip-flops as a register  Common register usages include Holding a data value output from an arithmetic circuit Holding a count value in a counter circuit  A common clock signal is typically used for each flip-flop in a register 35

36 Shift register  A register that provides the ability to shift its contents by a single bit  May be to the right or left (or possibly both) D Q Q Clock D Q Q D Q Q D Q Q In Out Q 1 Q 2 Q 3 Q 4 Shift right register 36

37 Shift right register  Data is shifted to the right in a serial fashion using the In input  Positive edge triggered  Contents of each flip-flop are transferred to the next flip-flop at each positive edge of the clock  Level sensitive devices would not be appropriate for this circuit InQ1Q1 Q2Q2 Q3Q3 Q4Q4 t0t t1t t2t t3t t4t t5t t6t t7t

38 Parallel-access shift register  Data transfer in computer systems is a common function  If the transfer is n-bits at a time, the transfer is said to be in parallel  If the transfer is 1-bit at a time, the transfer is said to be serial  To transfer data serially, data is loaded into a register in parallel (in one clock cycle) and then shifted out one bit at a time  Parallel-to-serial data conversion  If bits are received serially, after n clock cycles the contents of a register can be accessed in parallel as an n-bit item  Serial-to-parallel conversion 38

39 Parallel-access shift register QQQQ 3210 Clock Parallel input Parallel output Shift/Load Serial input D Q Q D Q Q D Q Q D Q Q 39

40 Counters  Special purpose arithmetic circuits used for the purpose of counting  Design circuits that can increment or decrement a count by 1  Counter circuits serve many purposes  Count occurrences of certain events  Generate timing intervals for controlling various tasks in a digital system  Track elapsed time between events  Often (but not always) built with T flip-flops because the toggle feature is naturally suited for implementing the counting operation 40

41 Up-counter with T flip-flops T Q Q Clock T Q Q T Q Q 1 Q 0 Q 1 Q 2 Q 0 Q 1 Q 2 Count

42 Down counter with T flip-flops T Q Q Clock T Q Q T Q Q 1 Q 0 Q 1 Q 2 Q 0 Q 1 Q 2 Count

43 Asynchronous counters  The previous counters are examples of asynchronous counters. Also called ripple counters.  Input clock is only connected to one flip-flop  Clocks for other flip-flops are (or are derived from) the outputs of the previous flip-flops  This form of counter is slow because the cascaded clocking scheme  The clock source ripples from stage-to-stage  The ripple effect is similar to that of a ripple carry adder circuit 43

44 Synchronous counters  Synchronous counters are built by clocking all the flip-flops at the same time (with a single clocking source)  Faster response than asynchronous counters  Synchronous counters with T flip- flops  Least significant bit, Q 0, changes every clock cycle  Bit one, Q 1, only changes when Q 0 =1  Bit two, Q 2, only changes when Q 0 =Q 1 =1 Q2Q2 Q1Q1 Q0Q Q 1 changes Q 2 changes 44

45 T flip-flop synchronous counter T Q Q Clock T Q Q T Q Q 1 Q 0 Q 1 Q 2 T Q Q Q 3 4-bit synchronous up counter 45

46 Enable and clear capability  It may be desirable to disable counting or clear the counter  Include an enable control signal  Use a flip-flop with asynchronous clear capability T Q Q Clock T Q Q Enable Clear T Q Q T Q Q 46

47 D flip-flop synchronous counter  A 4-bit up counter counts in the sequence 0,1,2,…,15,0,1…  The count is given by the flip-flop outputs Q 3 Q 2 Q 1 Q 0  The D inputs are given by: D 0 =Q 0  Enable D 1 =Q 1  Q 0  Enable D 2 = Q 2  Q 1  Q 0  Enable D 3 = Q 3  Q 2  Q 1  Q 0  Enable 47

48 Four-bit counter (D flip-flops) Q0Q0 Q1Q1 Q2Q2 Q3Q3 Carry output 48

49 Counters with parallel load  It is common for counters to begin a count with a zero value  An asynchronous clear input can be used for his purpose  It may be desirable for a counter to begin with a non-zero value  Adding circuitry to provide parallel load capability is necessary  A control input, load, is used to select a mode of operation  Load=0, circuit counts  Load=1, parallel load a new value into the counter 49

50 Parallel load counter load clock enableD0D0 D1D1 D2D2 D3D3 Q0Q0 Q1Q1 Q2Q2 Q3Q3 Carry output 50


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