Presentation on theme: "Lecture 6 CES 522 Latches and Flip-Flops Jack Ou, Ph.D."— Presentation transcript:
Lecture 6 CES 522 Latches and Flip-Flops Jack Ou, Ph.D.
Sequential Circuits New output are dependent on the inputs and the preceding values of outputs. Characteristic: output nodes are intentionally connected back to inputs. Basic sequential circuits: – Level Sensitive Circuits – Edge Sensitive Circuits
Latches Latches are level sensitive. Latches propagate values from input to output continuously. S sets Q =1; R sets Q=1 – Active low inputs are enabled by 0s. – Active high inputs are enabled by 1s.
SR Latch with NOR Gates t PDSQ =2 NOR gate delays. t PDRQ_ =1 NOR gate delay Forbidden State SR are trigger pulses which can return to zero once Q is set. Active High inputs
Definition Setup time: the time that the incoming data must be stable before the clock arrives Hold time: the length of time that the data remains stable after the clock arrives for proper operation If the data is stable before the setup time and continues to be stable after the hold time, the flop will work properly. If the data arrives within the period designated by the setup and hold times, the flop may or may not capture the correct value.
CLK-Q The delay from the time that the clock arrives to the point that the output stabilizes. In reality the data must arrive at the setup time before the clock hits and the output is valid after the CLK-Q delay.