2 Sequential Circuits Output depends on current input and past history of inputs. “State” embodies all the information about the past needed to predict current output based on current input. –State variables, one or more bits of information.
3 Describing Sequential Circuits State table –For each current-state, specify next-states as function of inputs –For each current-state, specify outputs as function of inputs State diagram –Graphical version of state table More on this next week
4 Clock signals Very important with most sequential circuits –State variables change state at clock edge.
5 Bistable element The simplest sequential circuit Two states –One state variable, say, Q HIGHLOW HIGH
6 Bistable element The simplest sequential circuit Two states –One state variable, say, Q LOWHIGH LOW
7 Analog analysis Assume pure CMOS thresholds, 5V rail Theoretical threshold center is 2.5 V
8 Analog analysis Assume pure CMOS thresholds, 5V rail Theoretical threshold center is 2.5 V 2.5 V
9 Analog analysis Assume pure CMOS thresholds, 5V rail Theoretical threshold center is 2.5 V 2.5 V 2.0 V 4.8 V 2.5 V2.51 V4.8 V0.0 V 5.0 V
10 Metastability Metastability is inherent in any bistable circuit Two stable points, one metastable point
11 Another look at metastability
12 “sube y baja” behavior
13 Why all the harping on metastability? All real systems are subject to it –Problems are caused by “asynchronous inputs” that do not meet flip-flop setup and hold times. –Details in Chapter-7 flip-flop descriptions and in Section 8.9 (later in quarter). Especially severe in high-speed systems – since clock periods are so short, “metastability resolution time” can be longer than one clock period. Many digital designers, products, and companies have been burned by this phenomenom.
14 Back to the bistable…. How to control it? –Screwdriver –Control inputs S-R latch
15 S-R latch operation Metastability is possible if S and R are negated simultaneously. (try it in Foundation)
22 D-latch timing parameters Propagation delay (from C or D) Setup time (D before C edge) Hold time (D after C edge)
23 Edge-triggered D flip-flop behavior
24 D flip-flop timing parameters Propagation delay (from CLK) Setup time (D before CLK) Hold time (D after CLK)
25 TTL edge-triggered D circuit Preset and clear inputs –like S-R latch 3 feedback loops –interesting analysis Light loading on D and C
26 CMOS edge-triggered D circuit Two feedback loops (master and slave latches) Uses transmission gates in feedback loops Interesting analysis method (Sec. 7.9)
27 Other D flip-flop variations Negative-edge triggered Clock enable Scan
28 Scan flip-flops -- for testing TE = 0 ==> normal operation TE = 1 ==> test operation –All of the flip-flops are hooked together in a daisy chain from external test input TI. –Load up (“scan in”) a test pattern, do one normal operation, shift out (“scan out”) result on TO.
29 J-K flip-flops Not used much anymore Don’t worry about them
30 T flip-flops Important for counters
31 Sequential PALs 16R8
32 One output of 16R8 8 product terms to D input of flip-flop –positive edge triggered, common clock for all Q output is fed back into AND array –needed for state machines and other applications Common 3-state enable for all output pins
33 PAL16R6 Six registered outputs Two combinational outputs (like the 16L8’s)
34 GAL16V8 Finally got it right Each output is programmable as combinational or registered Also has programmable output polarity
35 GAL16V8 output logic macrocell
36 GAL22V10 More inputs More product terms More flexibility
37 GAL22V10 output logic macrocell
38 Next time Sequential PLD timing ABEL sequential features Registers Counters Shift registers