1. IMPLEMENTATION OF µ - PROCESSOR DATA PATH
Project By:
Daniel Brauch
Elad Shabtai
Barak Schlosser

2. Project Goals
Designing and implementing the schematic and layout design of an 8 bit µProcessor data path , which will include an ALU Manchester carry look ahead and a barrel shifter.
Testing the design for accuracy and performance.

3. Data Path overall design

4. Applications:
The data path is the core element of every micro processor and thus included in every application that performs arithmetic calculations ,logic evaluation and data movement.

5. Implementation Notes :
The ALU will be built from a Manchester carry look ahead adder and eight 1 bit ALU.
The output of the ALU will be inserted into the shift register for shifting operations.
The barrel shifter can perform up to 3 bit shifts in a single combinational function.
The inputs for the ALU are valid on the rise of the clock.

6. Design Specifications:
ALU:
Inputs: two 8-bit words (A,B)
3-bit ALU controls.
3-bit shift controls.
1-bit clock.
* Cin bit will be generated from the ALU control bits
Output: 8-bit word (F), 1 carry out.
Functions:
A or B, A and B, A xor B, A + B,
A – B , B – A , Pass A, Pass B

7. Design Specifications:
Barrel Shifter:
Can multiply by 1, 2 , 4 or 8 by shifting left 0, 1 ,2 or 3 bits.
General:
Power supply: Vdd is set to 5 volts referenced to ground.
Size specifications: Final physical size must be optimized.
Time specifications: All data and control bits are set on the rise of the clock. The maximum propagation delay for all functions must be less than 100ns.

8. Manchester Carry

9. Manchester Carry Chain

10. Manchester Carry explanation
For each bit 2 values are calculated:
Pi = Ai XOR Bi
Gi = Ai AND Bi
On the rise of the clock the upper PMOS gates are closed and the bottom NMOS are open enabling the pull down of the carry out bar.
The Pi controls enables the propagation of the Cout signals.
The max propagation delay is caused by the pulling down of all the carry out bar signals.

11. Manchester Carry cont.
The main advantage of the Manchester chain is its small physical size.
In terms of propagation delay the Manchester chain is situated in the middle of the scale.

12. Comparison between different Full Adders

13. 1 bit ALU implementation
S2 S1
Cin B A’ A
MUX 4:1
FULL
ADDER
Out
LOGIC
S1 S0 A’ B’
MUX 4:1
XOR
AND OR

14. ALU control bits B - A 1 OR AND A + B XOR PASS B PASS A A - B S2 S1 S0
OPERATION
B - A 1 OR
AND
A + B
XOR
PASS B
PASS A
A - B
001 : OR
010 : AND
100 : XOR
CHAIN
XOR - 111
000 : B - A
111 : A - B
Equivalence
F.A
011 : A + B
110 : PASS A
101 : PASS B

15. MUX 4:1 implementation A B C D

16. 1 bit FULL ADDER implementation
SUM = A xor B xor C
C B A
** no need to compute carry out – calculated by Manchester carry look ahead

17. modules implementation
Tanner S-Edit
modules implementation

18. Manchester – module :

19. Simulation results : Carry all:
Carry last – worst case propagation ~10ns:

20. Barrel shifter – module :

21. Simulation results - shifting 01001011:

22. 1 bit ALU :

23. Data Path – modules : Calculate Cin : Define Cin : Shifter :
Alu1bit * bit output :
Choose output from Alu / Manchester :

24. 8 bit ALU - module : Including : Cin logic Manchester chain Alu
Cout logic

25. 8 bit ALU - design :

26. 8 bit ALU simulation - pass A (00000001) :

27. 8 bit ALU simulation - AND A (10001001) B (10000001) :

28. DataPath –module :

29. DataPath simulation : (A + B) * 4 A=00001010 B=00000011

30. DataPath simulation : (A + B) * 4 A=00001010 B=00000011

31. VHDL
Simulation

32. VHDL – simulation resaults :
Start – opCode 000 :
End – opCode 111 :

33. Advantages of design : Parallel implementation of calculations.
Minimal number of transistors in current implementation ~ 600 transistors
- Trivial implementation using mux 8*1 with scmos
implementation ~ 1300 transistors
- Less transistors thus low on power consumption
and faster in propagation ~ 40 ns

34. Milestones
Studying design options for the ALU, Manchester carry look ahead and shifter
- Due 01/06/04
Implementing all 3 units in gate level and testing them for correctness and performance
- Due 08/06/04
Combining units and testing overall design
- Due 15/06/04
Creating VHDL test bench and comparing designs
- Due 22/06/04
Grade : ?