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1 Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering Technique Mohab Anis, Shawki Areibi *, Mohamed Mahmoud.

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Presentation on theme: "1 Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering Technique Mohab Anis, Shawki Areibi *, Mohamed Mahmoud."— Presentation transcript:

1 1 Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering Technique Mohab Anis, Shawki Areibi *, Mohamed Mahmoud and Mohamed Elmasry VLSI Research Group, University of Waterloo, Canada * School of Engineering, University of Guelph, Canada

2 2 Presentation Outline Low Power Design in DSM Concept of sleep transistors Previous work Sizing the sleep transistor Bin-Packing technique Set-Partitioning technique Conclusion and extended work done

3 3 Why Low Power Design ? Growing market of mobile and handheld electronic systems. Difficulty in providing adequate cooling. Fans create noise and add to cost. Heat dissipation impacts packaging technology and cost Increasing standby time of portable devices. In DSM regimes, leakage power has become as big a problem as dynamic power

4 4 Concept of sleep transistors VXVX SLEEP HVT LVT Logic Block VXVX LVT Logic Block RI Modeling of a sleep transistor as a resistor MTCMOS technology is an increasingly popular technique to reduce leakage power Proper ST sizing is a key issue ST size Area, P dynamic, P leakage ST size Delay

5 5 First Approach [1] Single ST to support whole circuit Increase in interconnect resistance for distant blocks ST size to compensate added resistance Area P dynamic P leakage More significant in the DSM regime [1] S.Mutah et al. “1-V Power Supply High-Speed Digital Circuit Technology with Multi-Threshold Voltage CMOS,” IEEE J. of Solid-State Circuits, pp.847-853, 1995. SLEEP HVT LVT Logic Circuit

6 6 Second Approach [2] Single ST is sized according to a mutual exclusive discharge pattern algorithm. ST assignments are wasteful. Increase in interconnect resistance for distant blocks. ST size to compensate added resistance. P dynamic P leakage More significant in the DSM regime. G1G1 G9G9 G7G7 G8G8 G6G6 G4G4 G2G2 G3G3 G5G5 G 10 [2] J.Kao et al. “MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns”, in Proc. of 35 th DAC, pp. 495-500, Las Vegas, 1998

7 7 Sizing the sleep transistor Objective: Constant ST size, causing 5% degradation in circuit speed. (W/L) sleep = I sleep 0.05  n C ox (V dd -V tL )(V dd -V tH ) I sleep is chosen to be 250  A. (W/L) sleep  6 for 0.18  m CMOS technology V tL = 350mV, V tH = 500mV

8 8 4-bit CLA Adder

9 9 Preprocessing of Gate Currents Random I/Ps to CLA adder are applied, highest current discharge is monitored, and multiplied by corresponding switching activity Monitor the peak current value and time of occurrence + duration Currents are combined into single current I eq = max{I i }, when  I i in time  max{I i }

10 10 Timing Diagram T1=80psec T1+T2=210psec 79 65 260psec 120psec 0 0 11 22 33 43 54 65 54 43 33 22 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 12 18 24 30 37 43 49 55 61 67 73 79 73 67 61 55 49 43 37 30 24 18 12 6 0 0 0 0 0 0 0 I1 (G1): I2 (G2): I1 (G1) I2 (G2) T1 T2 G1 G2 F0=2 F0=4 time

11 11 Preprocessing Heuristic 1.Initialize current vectors 2.Set all Gates free; to move to sub-cluster; 3. For all gates in circuit If gate i is not clustered yet assign gate i to new cluster k update cluster current vector calculate max current, start, end time For all other gates in circuit If (gate j is not clustered yet) add current of gate j to cluster k If (combination  max current) append gate to cluster update cluster info set gate j locked in cluster k End For 4. Return all clusters formed.

12 12 Bin-Packing Technique Objective: Minimize the No. of used STs. Subject to: 1.  I eq  I max for any ST. 2. I eq are assigned only once.

13 13 Currents Assignment 240250  Currents (  A) G 1 G 2 G 3 G 4 G 9 G 10 G 11 G 12 G 13 G 15 G 17 G 19 G 20 G 21 G 22 G 24 G 25 G 26 G 27 G 28 G 5 G 6 G 7 G 8 G 14 G 16 G 18 G 23 Assigned Gates I EQ 1 I EQ 2 I EQ 5 I EQ 6 I EQ 3 I EQ 4 I EQ 7 Equivalent Currents 21 Sleep Transistors

14 14 Clustering of CLA adder

15 15 Set-Partitioning Technique Ground rail Sleep Device cavity Cell Vdd gnd Vdd gnd Cell Height G1G1 G3G3 G2G2 G5G5 G4G4 G7G7 G6G6 G8G8 G9G9 G 19 G 11 G 10 G 14 G 13 G 16 G 15 G 17 G 24 G 18 G 12 G 22 G 26 G 21 G 25 G 20 G 23 G 27 G 28 L min

16 16 Cost Function C j = ( w 1. C j 1 ) + ( w 2. C j 2 ) C j 1 = Sleep_Transistor max_current -  current i  i C j 2 =  d uv in a group S j GvGv GuGu GwGw d uv d wu d vw SjSj

17 17 Clustering Heuristic Create_Clusters ( ) 1.Calculate distances between all gates; 2.Initialize maxgates_per_cluster=n; 3.Create clusters with Single gates; 4.For cl=2; cl  maxgates_per_cluster Create_n_Gate_Cluster (cl) 5.For all clusters created calculate_cost ( ) Create_n_Gate_Clusters (cl) 1.For cluster of type cl create_new_cluster ( ) While not done Choose Gate with minimum distances If sum of currents  capacity append gate to newly created cluster End If If total gates within cluster  limit break; End While End For 2. Return newly created cluster

18 18 Set-Partitioning Technique Objective: Minimize  C j S j Subject to: 1.  of currents for S j  I max 2. Groups must cover all gates with no repetition.

19 19 Grouping of gates Ground rail Sleep Device cavity Cell Vdd gnd Vdd gnd Cell Height G1G1 G3G3 G2G2 G5G5 G4G4 G7G7 G6G6 G8G8 G9G9 G 19 G 11 G 10 G 14 G 13 G 16 G 15 G 17 G 24 G 18 G 12 G 22 G 26 G 21 G 25 G 20 G 23 G 27 G 28 L min

20 20 Computational Time BP/SP CPU TIME -200 0 200 400 600 800 1000 1200 1400 1600 1800 2000 28303161160204 Number of Gates Time (secs) SP CPU Time BP CPU Time

21 21 2 % 0 % 98 % 77 % 98, 76 % 9 % 8 % 87 % 71 % 86, 70 % 11 % 8 % 86 % 66 % 86, 67 % 19 % 9 % 85 % 35 % 85, 34 % 9 % 6 % 85 % 70 % 84, 69 % 7 % 5 % 87 % 78 % 87, 77 % P dynamic to [1] P dynamic to [2] P leakage to [1] P leakage to [2] ST_Area [1],[2] SP 2 % 0 % 99 % 89 % 99, 88 % 20 % 19 % 95 % 89 % 95, 89 % 17 % 14 % 93 % 83 % 93, 83 % 31 % 23 % 95 % 78 % 95, 78 % 18 % 16 % 92 % 85 % 92, 85 % 14 % 12 % 96 % 93 % 95, 92 % P dynamic to [1] P dynamic to [2] P leakage to [1] P leakage to [2] ST_Area [1],[2] BP 16020261303128No. of gates 27-channel interrupt controller C432 32-bit Single Error Correcting C499 4-bit 74181 ALU 6-bit Multiplier 32-bit Parity Checker 4-bit CLA adder BenchmarkREF Results (% Savings)

22 22 % Power Savings (Bin-Packing)

23 23 % Power Savings (Set-Partitioning)

24 24 % ST Area Saving (Bin-Packing)

25 25 % ST Area Saving (Set-Partitioning)

26 26 Conclusion BP technique cluster gates in MTCMOS circuits. P dynamic and P leakage are reduced by 15% and 90% compared to [1] and [2] respectively. SP takes routing complexity into consideration. P dynamic and P leakage are reduced by 11% and 77% compared to [1] and [2] respectively.

27 27 Extended Work Done A hybrid clustering technique that combines the BP and SP techniques is devised, to produce a more efficient and faster solution. Noise associated with ground bounce is taken as taken as a design criterion (< 50mV). Investigating effect of different ST sizes on circuit parameters. Investigating effect of the cost function weights w 1 and w 2 on circuit parameters.


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