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Nov. 8, 001Low-Power Design Digital Circuit Design for Minimum Transient Energy Vishwani D. Agrawal Circuits and Systems Research Lab, Agere Systems (Bell.

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Presentation on theme: "Nov. 8, 001Low-Power Design Digital Circuit Design for Minimum Transient Energy Vishwani D. Agrawal Circuits and Systems Research Lab, Agere Systems (Bell."— Presentation transcript:

1 Nov. 8, 001Low-Power Design Digital Circuit Design for Minimum Transient Energy Vishwani D. Agrawal Circuits and Systems Research Lab, Agere Systems (Bell Labs, Lucent Tech.) Murray Hill, NJ 07974 va@research.bell-labs.com http://cm.bell-labs.com/cm/cs/who/va Research Collaborators: M. L. Bushnell, Rutgers University R. Ramadoss, Lucent Microelectronics G. Parthasarathy, UC Santa Barbara

2 Nov. 8, 002Low-Power Design Power in a CMOS Gate VDD = 5V IDD Ground

3 Nov. 8, 003Low-Power Design Motivation Low power applications Remote systems (e.g., satellite) Portable systems (e.g., mobile phone) Methods of low power design Reduced supply voltage Adiabatic switching Clock suppression Logic design for reduced activity Reduce Hazards (40% in arithmetic logic) Software techniques Reference: Chandrakasan and Brodersen

4 Nov. 8, 004Low-Power Design Problem Statement Design a digital circuit for minimum transient energy consumption by eliminating hazards

5 Nov. 8, 005Low-Power Design Main Result: Theorem 1 For correct operation with minimum energy consumption, a Boolean gate must produce no more than one event per transition

6 Nov. 8, 006Low-Power Design Given that events occur at the input of a gate (inertial delay = d ) at times t 1 <... < t n, the number of events at the gate output cannot exceed Theorem 2 min ( n, 1 + ) t n – t 1 --------d t n - t 1 + d t n - t 1 + d t 1 t 2 t 3 t n t n + d t 1 t 2 t 3 t n t n + d time time

7 Nov. 8, 007Low-Power Design Minimum Transient Design Minimum transient energy condition for a Boolean gate: | t i - t j | < d Where t i and t j are arrival times of input events and d is the inertial delay of gate

8 Nov. 8, 008Low-Power Design Balanced Delay Method All input events arrive simultaneously Overall circuit delay not increased Delay buffers may have to be inserted 1 1 1 1 1 1 1 1 3 1 1 4?

9 Nov. 8, 009Low-Power Design Hazard Filter Method Gate delay is made greater than maximum input path delay difference No delay buffers needed (least transient energy) Overall circuit delay may increase 2 1 1 1 1 2 1 1 1 1 1? 3?

10 Nov. 8, 0010Low-Power Design Linear Program Variables: gate and buffer delays Objective: minimize number of buffers Subject to: overall circuit delay Subject to: minimum transient condition for multi-input gates AMPL, MINOS 5.5 (Fourer, Gay and Kernighan)

11 Nov. 8, 0011Low-Power Design Variables: Full Adder add1b 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0

12 Nov. 8, 0012Low-Power Design Objective Function Ideal: minimize the number of non- zero delay buffers Actual: sum of buffer delays

13 Nov. 8, 0013Low-Power Design Specify Critical Path Delay 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Sum of delays on critical path < maxdel _

14 Nov. 8, 0014Low-Power Design Multi-Input Gate Condition 1 1 1 1 0 0 0 0 0 0 d1 d2 d d1 - d2 < d d2 - d1 < d ________ d d

15 Nov. 8, 0015Low-Power Design AMPL Solution: maxdel = 6 2 1 1 1 1 1 2 1 2 2 1

16 Nov. 8, 0016Low-Power Design AMPL Solution: maxdel = 7 2 2 1 1 1 1 1 1 3 2

17 Nov. 8, 0017Low-Power Design AMPL Solution: maxdel > 11 2 3 1 1 1 1 4 3 5 _

18 Nov. 8, 0018Low-Power Design Power Estimates for add1b maxdel No.ofbuf. Power* with respect to Ref. Ref: model del. Ref: unit del. PeakAve.PeakAve. 67>112100.600.560.520.890.850.800.600.560.520.900.860.81 _ * Hsiao et al., ICCAD-97

19 Nov. 8, 0019Low-Power Design Power Calculation in Spice VDDVDD GroundGround Circuit Large C Open at t = 0 Ref.: M. Shoji, CMOS Digital Circuit Technology, Prentice Hall, 1988, p. 172. t Energy, E(t) E(t) = -- C VDD 2 - -- C V 2 ~ C VDD ( VDD - V ) 1 1 2 2 V V

20 Nov. 8, 0020Low-Power Design Power Dissipation of ALU4 Energy in nanojoules 0 1 2 3 4 5 6 7 0.00.5 1.0 1.5 2.0 microseconds Original ALU delay ~ 3.5ns Minimum energy ALU delay ~ 10ns 1 micron CMOS, 57 gates, 14 PI, 8 PO 100 random vectors simulated in Spice

21 Nov. 8, 0021Low-Power Design F0 Output of ALU4 Signal Amplitude, Volts 0 5 040 80 120 160 nanoseconds Original ALU, delay = 7 units (~3.5ns) Minimum energy ALU, delay = 21 units (~10ns) 5 0

22 Nov. 8, 0022Low-Power Design Some Comments J. Bentley: Path enumeration may be avoided by retiming type algorithms; Leiserson and Saxe, PhD theses M. Yannakakis: Use ellipsoid method if you can verify a solution in linear time; also try partitioning approach M. Wright: Use ILP

23 Nov. 8, 0023Low-Power Design References E. Jacobs and M. Berkelaar, “Using Gate Sizing to Reduce Glitch Power,” Proc. ProRISC/IEEE Workshop on Circuits, Systems and Signal Processing, Nov. 1996, pp. 183-188; also Int. Workshop on Logic Synthesis, May 1997. V. D. Agrawal, “Low-Power Design by Hazard Filtering,” Proc. 10th Int. Conf. VLSI Design, Jan. 1997, pp. 193-197. V. D. Agrawal, M. L. Bushnell, G. Parthasarathy, and R. Ramadoss, “Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method,” Proc. 12th Int. Conf. VLSI Design, Jan. 1999, pp. 434-439. Last two papers are available at website http://cm.bell- labs.com/cm/cs/who/va

24 Nov. 8, 0024Low-Power Design Conclusion Linear programming gives optimum design Analysis may reduce the number of constraints Technique can be applied to partitioned circuit An alternative min-flow formulation avoids path enumeration (approximate method) Transistor-sizing problem can be reformulated for area, delay and power reduction Glitch-free circuits have better timing properties Applications to CPU time reduction in programs and in project management for reduced cost

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