Download presentation

Presentation is loading. Please wait.

Published byCale Pearse Modified about 1 year ago

1
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 1 Programmable Logic zRegular logic yProgrammable Logic Arrays yMultiplexers/Decoders yROMs zField Programmable Gate Arrays yXilinx Vertex “Random Logic” Full Custom Design “Regular Logic” Structured Design

2
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 2 inputs AND array outputs OR array product terms Programmable Logic Arrays (PLAs) zPre-fabricated building block of many AND/OR gates yActually NOR or NAND y”Personalized" by making or breaking connections among gates yProgrammable array block diagram for sum of products form

3
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 3 example: F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A personality matrix 1 = uncomplemented in term 0 = complemented in term – = does not participate 1 = term connected to output 0 = no connection to output input side: output side: productinputsoutputs termABCF0F1F2F3 AB11–0110 B'C–010001 AC'1–00100 B'C'–001010 A1––1001 reuse of terms Enabling Concept zShared product terms among outputs

4
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 4 Before Programming zAll possible connections available before "programming" yIn reality, all AND and OR gates are NANDs

5
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 5 After Programming zUnwanted connections are "blown" yFuse (normally connected, break unwanted ones) yAnti-fuse (normally disconnected, make wanted connections)

6
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 6 notation for implementing F0 = A B + A' B' F1 = C D' + C' D AB+A'B' CD'+C'D AB A'B' CD' C'D ABCD Alternate Representation for High Fan-in Structures zShort-hand notation--don't have to draw all the wires ySignifies a connection is present and perpendicular signal is an input to gate

7
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 7 ABCF1F2F3F4F5F6 000001100 001010111 010010111 011010100 100010111 101010100 110010100 111110011 full decoder as for memory address bits stored in memory Programmable Logic Array Example zMultiple functions of A, B, C yF1 = A B C yF2 = A + B + C yF3 = A' B' C' yF4 = A' + B' + C' yF5 = A xor B xor C yF6 = (A xnor B xnor C)’

8
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 8 0 1 X 0 0 1 X 0 0 0 X X 0 0 X X D A B C minimized functions: W = A + B D + B C X = B C' Y = B + C Z = A'B'C'D + B C D + A D' + B' C D' ABCDWXYZ00000000000100010010001100110010010001100101111001101010011110111000100110011000101–––––11––––––ABCDWXYZ00000000000100010010001100110010010001100101111001101010011110111000100110011000101–––––11–––––– 0 0 X 1 0 1 X 1 0 1 X X 0 1 X X D A B C K-map for WK-map for X 0 1 X 0 0 1 X 0 1 1 X X 1 1 X X D A B C K-map for Y PLA Design Example zBCD to Gray code converter K-map for Z 0 0 X 1 1 0 X 0 0 1 X X 1 0 X X D A B C

9
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 9 not a particularly good candidate for PLA implementation since no terms are shared among outputs however, much more compact and regular implementation when compared with discrete AND and OR gates minimized functions: W = A + B D + B C X = B C' Y = B + C Z = A'B'C'D + B C D + A D' + B' C D' PLA Design Example (cont’d) zCode converter: programmed PLA

10
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 10 0 1 X 0 0 1 X 0 0 0 X X 0 0 X X D A B C minimized functions: W = X = Y = Z = ABCDWXYZ00000000000100010010001100110010010001100101111001101010011110111000100110011000101–––––11––––––ABCDWXYZ00000000000100010010001100110010010001100101111001101010011110111000100110011000101–––––11–––––– 0 0 X 1 0 1 X 1 0 1 X X 0 1 X X D A B C K-map for WK-map for X 0 1 X 0 0 1 X 0 1 1 X X 1 1 X X D A B C K-map for Y PLA Design Example zBCD to Gray code converter K-map for Z 0 0 X 1 1 0 X 0 0 1 X X 1 0 X X D A B C

11
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 11 0 1 X 0 0 1 X 0 0 0 X X 0 0 X X D A B C minimized functions: W = X = Y = Z = ABCDWXYZ00000000000100010010001100110010010001100101111001101010011110111000100110011000101–––––11––––––ABCDWXYZ00000000000100010010001100110010010001100101111001101010011110111000100110011000101–––––11–––––– 0 0 X 1 0 1 X 1 0 1 X X 0 1 X X D A B C K-map for WK-map for X 0 1 X 0 0 1 X 0 1 1 X X 1 1 X X D A B C K-map for Y PLA Design Example #1 zBCD to Gray code converter K-map for Z 0 0 X 1 1 0 X 0 0 1 X X 1 0 X X D A B C BC’

12
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 12 PLA Design Example #2 zMagnitude comparator 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 D A B C 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 D A B C 0 0 1 0 0 0 1 1 0 1 1 1 0 0 D A B C 0 1 1 1 0 0 1 1 0 0 0 0 0 0 1 0 D A B C K-map for EQ K-map for NE K-map for GT K-map for LT

13
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 13 multiplexerdemultiplexer4x4 switch control Multiplexer/Demultiplexer: Making Connections zDirect point-to-point connections between gates zMultiplexer: route one of many inputs to a single output zDemultiplexer: route single input to one of many outputs

14
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 14 two alternative forms for a 2:1 Mux truth table functional form logical form AZ0I01I1AZ0I01I1 I1I0AZ00000010010101101000101111011111I1I0AZ00000010010101101000101111011111 Z = A' I 0 + A I 1 Multiplexers/Selectors zMultiplexers/Selectors: general concept y2 n data inputs, n control inputs (called "selects"), 1 output yUsed to connect 2 n points to a single point yControl signal pattern forms binary index of input connected to output

15
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 15 z2:1 mux:Z = A' I0 + A I1 z4:1 mux:Z = A' B' I0 + A' B I1 + A B' I2 + A B I3 z8:1 mux:Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI3 + AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7 zIn general, Z = (m k I k ) yin minterm shorthand form for a 2 n :1 Mux 2 -1 I0 I1 I2 I3 I4 I5 I6 I7 A B C 8:1 mux Z I0 I1 I2 I3 A B 4:1 mux Z I0 I1 A 2:1 mux Z k=0 n Multiplexers/Selectors (cont'd)

16
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 16 control signals B and C simultaneously choose one of I0, I1, I2, I3 and one of I4, I5, I6, I7 control signal A chooses which of the upper or lower mux's output to gate to Z alternative implementation C Z A B 4:1 mux 2:1 mux I4 I5 I2 I3 I0 I1 I6 I7 8:1 mux Cascading Multiplexers zLarge multiplexers implemented by cascading smaller ones Z I0 I1 I2 I3 A I4 I5 I6 I7 B C 4:1 mux 2:1 mux 8:1 mux

17
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 17 C AB 0123456701234567 1010001110100011 S2 8:1 MUX S1S0 F Multiplexers as Lookup Tables (LUTs) z2 n :1 multiplexer implements any function of n variables yWith the variables used as control inputs and yData inputs tied to 0 or 1 yIn essence, a lookup table zExample: yF(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC = A'B'(C') + A'B(C') + AB'(0) + AB(1)

18
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 18 ABCF00010010010101101000101011011111ABCF00010010010101101000101011011111 C' C' 0 1 AB S1S0 F 01230123 4:1 MUX C' C' 0 1 F C AB 0123456701234567 1010001110100011 S2 8:1 MUX S1S0 Multiplexers as LUTs (cont’d) z2 n-1 :1 mux can implement any function of n variables yWith n-1 variables used as control inputs and yData inputs tied to the last variable or its complement zExample: yF(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC = A'B'(C') + A'B(C') + AB'(0) + AB(1)

19
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 19 zGeneralization zExample: F(A,B,C,D) implemented by an 8:1 MUX n-1 mux control variables single mux data variable four possible configurations of truth table rows can be expressed as a function of I n choose A,B,C as control variables multiplexer implementation I 0 I 1...I n-1 I n F....00011....10101 0I n I n '1 C AB 0123456701234567 1 D 0 1 D’ D D’ D’ S2 8:1 MUX S1S0 10101010 10 D A1 11011101 01100110 B C Multiplexers as LUTs (cont’d)

20
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 20 Announcements zWe took everyone on the wait list into the class yResult is that Tu labs are very crowded! yTh night lab is very light -- think of switching to get more TA face time! ySend email to pokai@berkeley.edu to request a lab changepokai@berkeley.edu zFirst HW due Friday at 2 PM … just before Lab Lecture yCS 150 hand-in box outside and just to the right of 125 Cory doors zSecond HW on class web site zUse ucb.class.cs150 newsgroup for lab, hw, course questions!

21
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 21 1:2 Decoder: O0 = G S’ O1 = G S 2:4 Decoder: O0 = G S1’ S0’ O1 = G S1’ S0 O2 = G S1 S0’ O3 = G S1 S0 3:8 Decoder: O0 = G S2’ S1’ S0’ O1 = G S2’ S1’ S0 O2 = G S2’ S1 S0’ O3 = G S2’ S1 S0 O4 = G S2 S1’ S0’ O5 = G S2 S1’ S0 O6 = G S2 S1 S0’ O7 = G S2 S1 S0 Demultiplexers/Decoders zDecoders/demultiplexers: general concept ySingle data input, n control inputs, 2 n outputs yControl inputs (called “selects” (S)) represent binary index of output to which the input is connected yData input usually called “enable” (G)

22
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 22 demultiplexer generates appropriate minterm based on control signals (it "decodes" control signals) Demultiplexers as General-Purpose Logic zn:2 n decoder implements any function of n variables yWith the variables used as control inputs yEnable inputs tied to 1 and yAppropriate minterms summed to form the function A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC C AB 0123456701234567 S2 3:8 DEC S1S0 “1”

23
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 23 F1 F2 F3 Demultiplexers as General-Purpose Logic (cont’d) zF1 = A' B C' D + A' B' C D + A B C D zF2 = A B C' D’ + A B C zF3 = (A' + B' + C' + D') AB 0A'B'C'D' 1A'B'C'D 2A'B'CD' 3A'B'CD 4A'BC'D' 5A'BC'D 6A'BCD' 7A'BCD 8AB'C'D' 9AB'C'D 10AB'CD' 11AB'CD 12ABC'D' 13ABC'D 14ABCD' 15ABCD 4:16 DEC Enable CD

24
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 24 0A'B'C'D'E' 1 2 3 4 5 6 7 S2 3:8 DEC S1S0 AB 01230123 S1 2:4 DEC S0 F 0 1 2A'BC'DE' 3 4 5 6 7 S2 3:8 DEC S1S0 E CD 0AB'C'D'E' 1 2 3 4 5 6 7AB'CDE Cascading Decoders z5:32 decoder y1x2:4 decoder y4x3:8 decoders 3:8 DEC 0 1 2 3 4 5 6 7ABCDE E CD S2S1S0S2 3:8 DEC S1S0

25
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 25 decoder 0n-1 Address 2 -1 n 0 1111 word[i] = 0011 word[j] = 1010 bit lines (normally pulled to 1 through resistor – selectively connected to 0 by word line controlled switches) j i internal organization word lines (only one is active – decoder is just right for this) Read-only Memories zTwo dimensional array of 1s and 0s yEntry (row) is called a "word" yWidth of row = word-size yIndex is called an "address" yAddress is input ySelected word is output

26
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 26 F0 = A' B' C + A B' C' + A B' C F1 = A' B' C + A' B C' + A B C F2 = A' B' C' + A' B' C + A B' C' F3 = A' B C + A B' C' + A B C' truth table ABCF0F1F2F3 0000010 0011110 0100100 0110001 1001011 1011000 1100001 1110100 block diagram ROM 8 words x 4 bits/word addressoutputs ABCF0F1F2F3 ROMs and Combinational Logic zCombinational logic implementation (two-level canonical form) using a ROM

27
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 27 ROM Structure zSimilar to a PLA structure but with a fully decoded AND array yCompletely flexible OR array (unlike PAL) n address lines inputs decoder 2 n word lines outputs memory array (2 n words by m bits) m data lines

28
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 28 ROM vs. PLA zROM yDesign time is short (no need to minimize output functions) yMost input combinations are needed (e.g., code converters) yLittle sharing of product terms among output functions ySize doubles for each additional input yCan't exploit don't cares yCheap (high-volume component) yCan implement any function of n inputs yMedium speed zPLA yDesign tools are available for multi-output minimization yThere are relatively few unique minterm combinations yMany minterms are shared among the output functions yMost complex in design, need more sophisticated tools yCan implement any function up to a product term limit ySlow (two programmable planes)

29
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 29 zPLAs: 100s of gate equivalents zFPGAs: 1000-10000s gates zLogic blocks yImplement combinational and sequential logic zInterconnect yWires to connect inputs and outputs to logic blocks zI/O blocks ySpecial logic blocks at periphery of device for external connections zKey questions: yHow to make logic blocks programmable? yHow to connect the wires? yAfter the chip has been fabbed Field-Programmable Gate Arrays

30
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 30 Tradeoffs in FPGAs zLogic block - how are functions implemented: fixed functions (manipulate inputs) or programmable? ySupport complex functions, need fewer blocks, but they are bigger so less of them on chip ySupport simple functions, need more blocks, but they are smaller so more of them on chip zInterconnect yHow are logic blocks arranged? yHow many wires will be needed between them? yAre wires evenly distributed across chip? yProgrammability slows wires down – are some wires specialized to long distances? yHow many inputs/outputs must be routed to/from each logic block? yWhat utilization are we willing to accept? 50%? 20%? 90%?

31
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 31 Xilinx 4000 Series Programmable Gate Arrays zCLB - Configurable Logic Block y5-input, 1 output function yor 2 4-input, 1 output functions yoptional register on outputs zBuilt-in fast carry logic zCan be used as memory zThree types of routing ydirect ygeneral-purpose ylong lines of various lengths zRAM-programmable ycan be reconfigured

32
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 32 The Xilinx 4000 CLB

33
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 33 Two 4-Input Functions, Registered Output

34
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 34 5-Input Function, Combinational Output

35
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 35 CLB Used as RAM

36
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 36 Xilinx 4000 Interconnect

37
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 37 Xilinx FPGA Combinational Logic Examples zKey: General functions are limited to 5 inputs y(4 even better - 1/2 CLB) yNo limitation on function complexity zExample 2-bit comparator: A B = C D and A B > C D implemented with 1 CLB (GT)F = A C' + A B D' + B C' D' (EQ)G = A'B'C'D'+ A'B C'D + A B'C D'+ A B C D zCan implement some functions of > 5 input

38
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 38 CLB 5-input Majority Circuit CLB 7-input Majority Circuit CLB 9 Input Parity Logic Xilinx FPGA Combinational Logic zExamples yN-input majority function: 1 whenever n/2 or more inputs are 1 yN-input parity functions: 5 input/1 CLB; 2 levels yield 25 inputs!

39
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 39 Xilinx FPGA Adder Example zExample y2-bit binary adder - inputs: A1, A0, B1, B0, CIN outputs: S0, S1, Cout Full Adder, 4 CLB delays to final carry out 2 x Two-bit Adders (3 CLBs each) yields 2 CLBs to final carry out

40
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 40 Combinational Logic Implementation Summary zRegular Logic Structures yProgrammable Logic Arrays xProgrammable connections: AND-OR (NOR-NOR) Arrays yMultiplexers/decoders xMultipoint connections for signal routing xLookup Tables yROMs xTruth table in hardware yField Programmable Gate Arrays (FPGAs) xProgrammable logic (LUTs, Truth Tables) and connections yAdvantages/disadvantages of each

Similar presentations

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google