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컴퓨터구조론 교수 채수환. 교재 Computer Systems Organization & Architecture John D. Carpinelli, 2001, Addison Wesley.

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Presentation on theme: "컴퓨터구조론 교수 채수환. 교재 Computer Systems Organization & Architecture John D. Carpinelli, 2001, Addison Wesley."— Presentation transcript:

1 컴퓨터구조론 교수 채수환

2 교재 Computer Systems Organization & Architecture John D. Carpinelli, 2001, Addison Wesley

3 평가방법 중간고사 40% 학기말 고사 40% 레포트 및 출석 20% 계 100% 단 결석 ¼ 이상은 F 학점

4 What must you do as a junior student Improve your grade up to at least 3.5/4.5. Cultivate your English ability. Make good relationship with your friends. Think your future seriously. Be an expert in your field. Be flexible.

5 Chapter 1 Digital Logic Fundamentals Boolean Algebra Basic Combinatorial Logic More Complex Combinatorial Components Combinatorial Circuit Design Basic Sequential Components More Complex Sequential Components Real World Example: PLD

6 1.1 Boolean Algebra Basic Functions AND  NAND OR  NOR NOT XOR  XNOR (or Equivalence) Table 1.3: All possible binary Boolean functions

7 1.1 Boolean Algebra( 계속 ) Manipulation of Boolean Algebra DeMorgan ’ s Law Minterm Karnaugh map(K-map)

8 1.1 Boolean Algebra( 계속 ) DeMorgan ’ s Law It allows a digital designer to convert an AND function to an equivalent OR function and vice versa. (ab) ’ =a ’ +b ’ (a+b) ’ =a ’ b ’ Example: (xy ’ +yz) ’ =(xy ’ ) ’ (yz) ’ =(x ’ +y)(y ’ +z ’ ) =x ’ y ’ +x ’ z ’ +yy ’ + yz ’ = x ’ y ’ +x ’ z ’ + yz ’

9 1.1 Boolean Algebra( 계속 ) Minterm Each possible AND set of input values If there are two input values, x and y, there are four possible minterms: x ’ y ’, x ’ y, xy ’, xy

10 1.1 Boolean Algebra( 계속 ) K-map (Karnaugh-map) A useful device for minimizing logic

11 Figure 1.1 K-maps

12 1.1 Boolean Algebra( 계속 ) K-map The ordering of K-map inputs: Gray code A Gray code is a reflected code.

13 Figure 1.2 Gray code sequence generation

14 1.1 Boolean Algebra( 계속 ) Grouping on K-map Prime Implicants(PI) Essential Prime Implicants(EPI): groups which include cells that covered by only one group.

15 Figure 1.3 (xy’+yz)’

16 Figure 1.4 More complex function

17 1.1 Boolean Algebra( 계속 ) Don ’ t care When some patterns of input values will never occur, it is called don ’ t care condition. We can treat the don ’ t care values as either 0 or 1, whichever makes it easier to group the minterms.

18 Figure 1.5 A 7-segment LED driver

19 1.2 Basic Combinatorial Logic Gates: digital components that implement the logic functions. AND OR NOR NOT NAND NOR XNOR

20 Figure 1.6 Logic Symbols

21 1.2 Basic Combinatorial Logic(continued) The gates can be combined to realize more complex functions. There are some realization ways for a given complex functions depending on the conditions.

22 Figure 1.7 Two realization of the function wx’+x’z’+w’xyz

23 1.2 Basic Combinatorial Logic(continued) Buffers: Buffers do not perform any operations on its input. Regular buffer: to boost the current of input to a higher level Tri-state buffer: it has a data input, just like the regular buffer, but also an enable input, E. If E is disable state, it produces a high impedance output.

24 Figure 1.8 Logic symbols for buffers Buffers: Regular buffers(simply buffers): for boosting the current Tri-state buffers: enable, high-impedance

25 1.3 More Complex Combinatorial Components Multiplexer(MUX) It chooses one of its data inputs and passes it through to its output. Select signals are needed for select a data input

26 Figure 1.9 (a) Internal configuration of 4-to-1 MUX

27 Figure 1.9 (b) Schematic representation with an active high enable signals

28 Figure 1.9 (c) Schematic representation with an active low enable signals

29 Figure 1.10 A 4-to-1 MUX constructed using 2-to-1 MUXs

30 1.3 More Complex Combinatorial Components(continued) Decoder It accepts a value and decodes it. It has n inputs and 2 n outputs, numbered from 0 to 2 n – 1.

31 Figure 1.11 Internal Configuration of a 2-to-4 decoder

32 Figure 1.11 (b) Schematic representation with an active high enable signals

33 Page 19, Figure 1.11 (c) Schematic representation with an active low enable signals

34 1.3 More Complex Combinatorial Components(continued) Encoder It is the exact opposite of the decoder. It receives 2 n inputs and outputs an n-bit value corresponding to the input value.

35 Figure 1.12 (a) Internal Configuration of a 4- to-2 encoder

36 Figure 1.12 (b) Schematic representation with an active high enable signals

37 Figure 1.12 (c) Schematic representation with an active low enable signals

38 1.3 More Complex Combinatorial Components(continued) Priority encoder The encoder works if zero or one inputs are active, but fails. A priority encoder works just like a regular encoder, with one exception, Whenever more than one input is active, the output is set to corresponding to the highest active input.

39 Figure 1.13 (a) A 4-to-2 priority encoder

40 Figure 1.13 (b) and (c) The other 4-to-2 priority encoder and its truth table

41 1.3 More Complex Combinatorial Components(continued) Comparator It compares two n-bit binary values to determine which is greater, or if they are equal.

42 Figure bit comparator

43 Figure bit comparator with propagated inputs

44 Figure 1.16 n-bit comparator constructed using 1-bit comparators with propagated inputs

45 1.3 More Complex Combinatorial Components(continued) Adder Adders are most commonly used, not only to perform addition, but also to perform subtraction, multiplication, and division. Half adder Full adder Ripple adder Carry lookahead addeer

46 Figure 1.17 A half adder

47 Figure 1.18 a full adder

48 Figure bit adder constructed using full adders

49 1.3 More Complex Combinatorial Components(continued) Full subtracter A full subtracter(Figure 1.20) Two ’ s complement addition By doing this, a CPU may use a parallel adder for addition and subtraction.

50 Figure 1.20 A full subtracter

51 1.3 More Complex Combinatorial Components( 계속 ) Memory It is a group of circuit used to store data. Address inputs Data lines Classes of memory chips depending on volatility ROM RAM

52 Figure 1.21 ROM and RAM

53 1.4 Combinatorial Circuit Design BCD to 7-Segment Decoder

54 Figure 1.22 A 7-Segment LED display

55 Figure 1.23 (a) K-maps for designing segments

56 Figure 1.23 (b) Circuits to implement segments b and c

57 Figure 1A : LEDS (a) active high (b) active low

58 1.4 Combinatorial Circuit Design(continued) A sorter

59 Figure 1.24 (a) A two-input compare- and –swap module

60 Figure 1.24 (b) four-input data sorter

61 1.5 Basic Sequential Components The most fundamental components are latch and flip-flop Latch: level-triggered Flip-Flop: edge-triggered Triggering Positive Negative Clock It is used to synchronize the flow of data in a digital system

62 Figure 1.25 clock sequence

63 1.5 Basic Sequential Components(continued) D latch and D F-F It has one input, D, and a clock input. The value of D becomes output, Q, after some delay. LD signal: It must be high as the clock changes from 0 to 1 in order for the data to be loaded into the F-F.

64 Figure 1.26 (a) Positive-edge triggered D F-F

65 Figure 1.26 (b) Positive-level triggered D latch

66 Figure 1.27 Positive level triggered D latch with set and clear

67 Figure 1.28 SR latch

68 1.5 Basic Sequential Components(continued) JK-FF It resolves the problem of undefined when SR=11

69 Figure 1.29 J-K F-F

70 Figure 1.30 T F-F

71 1.5 Basic Sequential Components(continued) Flip-flops and latches may be combined in parallel to store data with more than one bit.

72 Figure bit D F-F

73 1.6 More Complex Sequential Components Counters It stores a binary value and, when signaled to do so, arithmetically increases or decreases its value. Ripple counter Up/down counter

74 Figure bit Counter

75 Figure bit up/down counter

76 1.6 More Complex Sequential Components Shift registers it can shift data one bit position to the right or left. It is particularly useful for certain hardware multipliers and dividers.

77 Figure bit left-shift register

78 1.7 Real World Example PLA PAL PLD FPGA

79 Figure 1.35 PLA programmed b=x2’+x1’x0’+x1x0 and c=X2+X1’+X0

80 Figure 1.36 PAL programmed b=x2’+x1’x0’+x1x0 and c=X2+X1’+X0


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