교재 Computer Systems Organization & Architecture John D. Carpinelli, 2001, Addison Wesley
평가방법 중간고사 40% 학기말 고사 40% 레포트 및 출석 20% 계 100% 단 결석 ¼ 이상은 F 학점
What must you do as a junior student Improve your grade up to at least 3.5/4.5. Cultivate your English ability. Make good relationship with your friends. Think your future seriously. Be an expert in your field. Be flexible.
Chapter 1 Digital Logic Fundamentals Boolean Algebra Basic Combinatorial Logic More Complex Combinatorial Components Combinatorial Circuit Design Basic Sequential Components More Complex Sequential Components Real World Example: PLD
1.1 Boolean Algebra Basic Functions AND NAND OR NOR NOT XOR XNOR (or Equivalence) Table 1.3: All possible binary Boolean functions
1.1 Boolean Algebra( 계속 ) Manipulation of Boolean Algebra DeMorgan ’ s Law Minterm Karnaugh map(K-map)
1.1 Boolean Algebra( 계속 ) DeMorgan ’ s Law It allows a digital designer to convert an AND function to an equivalent OR function and vice versa. (ab) ’ =a ’ +b ’ (a+b) ’ =a ’ b ’ Example: (xy ’ +yz) ’ =(xy ’ ) ’ (yz) ’ =(x ’ +y)(y ’ +z ’ ) =x ’ y ’ +x ’ z ’ +yy ’ + yz ’ = x ’ y ’ +x ’ z ’ + yz ’
1.1 Boolean Algebra( 계속 ) Minterm Each possible AND set of input values If there are two input values, x and y, there are four possible minterms: x ’ y ’, x ’ y, xy ’, xy
1.1 Boolean Algebra( 계속 ) K-map (Karnaugh-map) A useful device for minimizing logic
1.1 Boolean Algebra( 계속 ) Don ’ t care When some patterns of input values will never occur, it is called don ’ t care condition. We can treat the don ’ t care values as either 0 or 1, whichever makes it easier to group the minterms.
1.2 Basic Combinatorial Logic(continued) The gates can be combined to realize more complex functions. There are some realization ways for a given complex functions depending on the conditions.
Figure 1.7 Two realization of the function wx’+x’z’+w’xyz
1.2 Basic Combinatorial Logic(continued) Buffers: Buffers do not perform any operations on its input. Regular buffer: to boost the current of input to a higher level Tri-state buffer: it has a data input, just like the regular buffer, but also an enable input, E. If E is disable state, it produces a high impedance output.
Figure 1.8 Logic symbols for buffers Buffers: Regular buffers(simply buffers): for boosting the current Tri-state buffers: enable, high-impedance
1.3 More Complex Combinatorial Components Multiplexer(MUX) It chooses one of its data inputs and passes it through to its output. Select signals are needed for select a data input
Figure 1.9 (a) Internal configuration of 4-to-1 MUX
Figure 1.9 (b) Schematic representation with an active high enable signals
Figure 1.9 (c) Schematic representation with an active low enable signals
Figure 1.10 A 4-to-1 MUX constructed using 2-to-1 MUXs
1.3 More Complex Combinatorial Components(continued) Decoder It accepts a value and decodes it. It has n inputs and 2 n outputs, numbered from 0 to 2 n – 1.
Figure 1.11 Internal Configuration of a 2-to-4 decoder
Figure 1.11 (b) Schematic representation with an active high enable signals
Page 19, Figure 1.11 (c) Schematic representation with an active low enable signals
1.3 More Complex Combinatorial Components(continued) Encoder It is the exact opposite of the decoder. It receives 2 n inputs and outputs an n-bit value corresponding to the input value.
Figure 1.12 (a) Internal Configuration of a 4- to-2 encoder
Figure 1.12 (b) Schematic representation with an active high enable signals
Figure 1.12 (c) Schematic representation with an active low enable signals
1.3 More Complex Combinatorial Components(continued) Priority encoder The encoder works if zero or one inputs are active, but fails. A priority encoder works just like a regular encoder, with one exception, Whenever more than one input is active, the output is set to corresponding to the highest active input.
Figure 1.15 1-bit comparator with propagated inputs
Figure 1.16 n-bit comparator constructed using 1-bit comparators with propagated inputs
1.3 More Complex Combinatorial Components(continued) Adder Adders are most commonly used, not only to perform addition, but also to perform subtraction, multiplication, and division. Half adder Full adder Ripple adder Carry lookahead addeer
Figure 1.19 4-bit adder constructed using full adders
1.3 More Complex Combinatorial Components(continued) Full subtracter A full subtracter(Figure 1.20) Two ’ s complement addition By doing this, a CPU may use a parallel adder for addition and subtraction.
1.5 Basic Sequential Components The most fundamental components are latch and flip-flop Latch: level-triggered Flip-Flop: edge-triggered Triggering Positive Negative Clock It is used to synchronize the flow of data in a digital system
1.5 Basic Sequential Components(continued) D latch and D F-F It has one input, D, and a clock input. The value of D becomes output, Q, after some delay. LD signal: It must be high as the clock changes from 0 to 1 in order for the data to be loaded into the F-F.