1. Future IC Test Challenges Quality, Cost and Time to Market
Korea test conference workshop 2014
Jin-Soo Ko
Teradyne Inc.
Korea test workshop Oct Jin-Soo Ko

2. Mobile Device challenges
Fast Ramps
Essentially full volume from product launch for high profile new products
Must bring up new silicon process at the same time (14nm, FinFET)
Yield must be good to reduce cost but defect rate must be extremely low
Number of units sold during the first weekend of product introduction
COT is important but getting to market quickly with the best quality is what really counts!
Silicon
Samples
Mass Production
Days
Weeks
“Zero” DPM

3. Advanced silicon process and VDD

4. ITRS semiconductor roadmap
Roadmap for Gate Length and Supply Voltage

5. Market trends driving IC test
Fast Time To Market
Less Than 15 Days Si to Samples
Functional Integration
Large Test Lists
Collaborative Development
Quality
<100 DPM For Mobility Devices
Complex Flows
Increased Device Configuration and Repair
COT Pressures
Higher Multisite, Concurrent Test, Datalog overhead
Faster Time To Volume
>1M devices within 2 Months

6. What is the most important for test? (from itrs)
Cost of Test, Time To Market and Test Quality are equally Important
Why?
Test Costs are a small part of the overall cost to make an IC. Focusing only on this does not increase profit much
In the mobile space, being first to market captures more market share which increases profit the most
Equipment manufacturers will not accept poor IC quality.
High quality devices have higher value and bring more profit.
Higher yield also means lower overall cost.
Korea test workshop Oct Jin-Soo Ko

7. Cost of test(COT) Cost trends (ITRS)
ATE Capital costs are actually decreasing
This also increases Time To Market
“consumable” items like probe cards and sockets are increasing in costs
Korea test workshop Oct Jin-Soo Ko

8. Cost of test(COT) Cost trends (ITRS) Very dependent on DFT Technology
Could potentially eliminate System Level Test insertion to lower costs
Korea test workshop Oct Jin-Soo Ko

9. Design complexity and scan depth
Compression contained ATE memory requirements growth from 2000 to 2010, but is approaching theoretical limits
Reduced Pin Count Test Will Drive Memory Requirements Higher
Also puts strain on datalog and post processing features
Current Industry Practice

10. More Scan Testing = More Test Time
As devices get more complex and scan compression can’t keep up, test times will get longer
Increased ATE efficiency keeps COT flat
Higher Site count (Multi-site Testing) is the most efficient way to reduce costs
Similar to memory test
3X scan test time in 5 years due to higher gate count

11. COT - Multi-site and Concurrent test and TTR
PMIC
PMIC BT FM
PMIC RF
Tx/Rx
ABB FM BT
PMIC RF
Tx/Rx
ABB FM BT
Time
PMIC RF
Tx/Rx
ABB FM BT
PMIC RF
Tx/Rx
ABB FM BT BB BB RF
USB RF FM
~11s (estimated)
=> 35% TTR (estimated)
Test Throughput improvement
N=16 sites (PTE 0.98)
35% test time reduction by concurrent test,
Multi-site test throughput 0.98xN site
Concurrent test throughput 1/( )
Throughput = 0.98x16/(1-0.35) = 24.12 BT
USB
*Shared device functions prevent some
concurrency
~17s
Korea test workshop Oct Jin-Soo Ko

12. Concurrent test programming and debug tool
Timeline viewer
Serial Test Flow
Tests
Block A
Block B
Block C
Block D
Block E
Block F
Test
Time
Initial
Full Functional
Tests
Block A
Block B
Block C
Block D
Block E
Initial
Block F
Test
Time
Full Functional
Concurrent Test Flow
Development Challenges
Common bus/pins
Shared test resources
Flow manipulation
Multi-site implementation
Adaptive test & Retest
Debug tools
Different screens shots for A and B

13. Multi-site Test Roadmap
FLEX
8-site CD, DVD Player Processor SOC test solution
16-site
Mobile A/V Processor SOC test solution
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2 or 4-site
32-site
UltraFLEX
Catalyst/Tiger
4-site Optical Disk Drive SOC test solution
8-site
UltraFLEX-HC
16-32-site >1000 pin count SOC device test HIB design solution using new high density (x2 ~ x4) digital, AC, and DC options
UltraFLEX-XD
2012
2014
TIU+DSA
>> 32//
2016
Multi-site capability is the key strategy to achieve low COT
4-site codec in 2001
8-site CDP/DVDP in 2004
16-site Mobile A/V processor in 2007
32-site Mobile A/V processor in 2009
16 -site Mobile Application Process in 2011
32-siite from 2015 ?
Korea test workshop Oct Jin-Soo Ko 13

14. COT - Multi Site Count test roadmap
Number of Sites
“High Mix” = many different device types tested in small lots
“Low Mix” = only a few device types tested in large lots

15. COT - Multi Site Vs. Parallel test efficiency
Korea test workshop Oct Jin-Soo Ko

16. AWG Sequence for Pattern Based Programming
The entire AWG Plots
BUCK1
BUCK2
BUCK3
BUCK4
BUCK5
BUCK6
BUCK7
VIN
MCU
LNR1
LNR2
LDR1
LDR2
LDR3
The scale reference is different in each plots.
Korea test workshop Oct Jin-Soo Ko

17. COT - Chip to Chip Data
Korea test workshop Oct Jin-Soo Ko

18. COT - Pattern Based Programming Test Time
BUCK ,BUCK_DVS and LDO,LDO_LDR Test time reduction
Items
Before[mS]
After[mS]
TTR[%]
BUCK
50.04
BUCK_DVS
66.67
LDO_LDR
60.0
LDO
92.404
Total
57.36
Korea test workshop Oct Jin-Soo Ko

19. COT - Upgrade test computer
Next generation tester computer
Load & Validate time improvement up to ~ 20%
Average Runtime Improvement of ~ 4% to 20%
Windows 7
33% increase in application memory
Microsoft Office 2010
Interoperability between Excel 2010 and Excel 2003
New Sheet-Grouping and Navigation Features
Benchmark Test Summary:
Tera1 Windows7
Market Segment
Run Time
PMIC
4.75%
MAP+ DBB
4.30%
Connectivity 5%
CODEC
11%
Cellular
20%

20. COT – Buy Rate down Test equipment is already very efficient.
Equipment Capital Buy Rate down
“Buy Rate” = ATE Cost / IC Revenue 1%
2013
$1.00 of IC revenue = $0.005 of test capital
Lowering Cost of Test 10% only increases profit by 0.05%
Raising Yield from 95% to 96% increases profit by > 1% (Much better investment!)
Winning new socket increases market share (Best investment!)
Buy Rate
“Front End” Costs
Test equipment is already very efficient.
Most new “test” investment focused on Time To Market and Quality to improve IC revenue and market share
“Back End” Costs
Korea test workshop Oct Jin-Soo Ko

21. What is this and why you should care?
Time to market (TTM)
What is this and why you should care?
Directly impact to market share and profits
Smart phone market is never wait for the delay of test.
Korea test workshop Oct Jin-Soo Ko

22. TTM - How to get fast Time to market ?
Industry standard test system and SW capability
Integration with design and bench test
Advanced ATE SW tools for Time to Market
Design
Simulation
On-Tester Debug/ Characterization (hours/minutes)
Timing/Levels
Mixed Signal
Repeatability
Correlation
Pattern & Test program. Gen.
events
transactions
ATPG
STDF
“off tester” tools
“on tester” tools
Failure Analysis / Yield Enhancement
EDA-based Pattern Viewer
Simultaneous display of EDA and tester information
Diagnose Physical Device Faults
Design  Test  Design Loop
EDA Systems
ATPG Tools
Adaptive Test
Real-time Fault Isolation
Physical Failure Analysis
“Big Data” Storage
Korea test workshop Oct Jin-Soo Ko

23. TTM - Multi-sheet use model
= no more manual merging of sub programs
Separate test code & data for each sub program
Tied together at the Job List Sheet
Multi-Sheet Model
Sub-Program A
Different screens shots for A and B
Enabler for independent development
Reduces time to integrate
Sub-Program B

24. TTM - RF tools- LTE-A TX signal debug tool
IG-XL 7.30
ESA 2.0
3GPP LTE
TD-SCDMA
802.11n 4x4 MIMO
VSA 10.01
1 port vector
Power de-embedding
Signal sheet support
Smith charting
IG-XL 7.40
ESA 2.5
3GPP LTE Update
Bluetooth 3.0
VSA 11
IG-XL
ESA 3.0
LTE 8.9
VSA12
IG-XL 8.10
ESA 3.5
LTE-A (R10)
802.11ac
VSA 14
IG-XL 8.20
ESA 4.0
LTE-A (100MHz)
802.11ac (160MHz)
802.11ac (80+80)
BT 4.0 (LE)
VSA 16
90% reduction in VSA instance creation times
Need to add features beyond
Korea test workshop Oct Jin-Soo Ko

25. TTM - How To Do Protocol Level Test?
Integrated Mobile Device
CPU
Mem
I/F
DRAM Emulation Engine
JTAG Protocol Engine
JTAG
USB
USB Protocol Engine
DSP BB
Proc
Power Mgmt
Functions
DC Test
Resources
Audio / BB
AC Test
GPS 4G
WiFi
FM/TV
Modulation Domain RF
Protocol Level
ATE
Protocol Synchronization & Communication
Match an independent part of the tester to each interface
Match the device’s frequency, timing, etc.
Communicate natively in the “Language” of the port

26. Integrated Mobile Device
TTM - Protocol Aware
Complex Device Architecture
“Stored Response” ATE
Integrated Mobile Device
CPU
DRAM
I/F
Flash
JTAG
USB
DSP BB
Proc
Power Mgmt
Functions
Audio / BB
GPS
3G RF
WiFi
FM/TV
Tries to Test
Write.jtag ( ADDR: 04h, DATA: 55h)
Read.jtag (ADDR: 0Ah, DATA  read_var)
Need to add features beyond
Protocol Definition Editor
For defining and modifying protocols
Protocol Studio
For online debug of protocol transactions
Transaction results Debug displays Data capture setups
Module management Port Properties

27. Device Trends drive New test needs
Quality of test (QOT) – Technical challenges
Device Trends drive New test needs
Mapping Physical and electrical defects
Lithography
More scan testing with failure capture and diagnosis capability = More Patterns, especially at the start of the product life
Need to capture high volumes of scan data for offline analysis
Higher speed Data IO
High Speed Characterization capability with phenomenal Timing accuracy.
Ability to use higher performance standard digital to screen devices in production to augment DFT. DFT-Only approach has more risk as data rates increase.
Lower voltage
Device Supplies < 700mV require excellent accuracy. Huge Current steps cannot cause glitches
More complex RF Standards
Precise measurement of complex RF constellations
Larger number of RF measurements
Device Re-configuration
More Complex Test Programs to do different testing per site
New Packaging
Ability to do a complete test at probe
System Level Test capability for stacked die
Power Supply Stability Example
Test Flow
Site 1
Site 2

28. Quality of test (QOT) – Technical challenges
DC Challenges
Korea test workshop Oct Jin-Soo Ko

29. QOT - ITRS semiconductor roadmap for gate length and supply voltage
Supply Voltage levels will continue to decrease
New test requirements for power supplies to be stable and accurate
Need very critical DIB PI simulation and design process

30. Test Quality - Dc power VDD accuracy & droop
Power Supply Stability Example
AP requires many supplies
Core supplies
IO Supplies
Requirements are very different
Core: Accuracy, dynamic performance
IO: Wider voltage range, more connections
All device supplies will have some momentary “droop” when scan patterns are started.
Too large a “droop” will cause good parts to fail, reducing yield
Network Processor Example
Single Supply Solution
Ganged Solution .

31. Quality of test (QOT) – Technical challenges
RF Challenges
Korea test workshop Oct Jin-Soo Ko

32. Wireless Industry Trends
Increase Demand for Higher Data Rate & Connectivity
Overall mobile data traffic is expected to grow at a 61% CAGR to Exabytes per month by 2018
Migration to LTE-Advanced occurring in all market segment (high and low end)
New standards require 2x-3x more active RF device ports
Demand for higher performance and high site count test capability
Internet-of-things driving rapid growth of MCU + RF segment
Shrinking Device Size While Increasing Complexity
Mobile IC’s moving away from conventional package to wafer-level package technologies (Flip-chip, WLCSP, FOWLP)

33. LTE Test Challenges – Modulation Quality
Ideal Signal
Measured Signal
Test Limit
When Testing an RF Device, we want to measure how much the signal is corrupted by things like:
Phase Noise
Signal Imbalance
Other noise and distortion
All of these errors are combined into Error Vector Magnitude. It is a clear way to measure RF signal quality
To do production testing, the EVM of the tester must be much better than the Device Under Test
LTE Base Station = 13.5%
LTE User Equip 12.5%
802.11ac = 11.22%
LTE Base Station = 9.0%
802.11ac = 3.98%
802.11ac = 2.51%
16-QAM
802.11a/g, LTE
64-QAM
802.11a/g/n; LTE-A
256-QAM ac
- Device Spec Limit

34. Example of How Tester Errors Become More Critical for New RF Standards
The plot below shows the effects of IQ skew Imbalances (modulation signals being out of phase)
If testing an actual device, the skew, gain and other distortion would contribute to the EVM error.
802.11ac 160M
EVM Limit = 2.51%
802.11ac 160M
LTE-A 100M
Can’t Test! X
These charts a made up of many different types of standards.
It does not matter what standard we’re testing the effect of BW on a signal effects all standards in a similar way.
Good Test Margin
LTE 20M
Skew
Tester with 0.5% EVM Test Capability
Tester with 1-2% EVM Test Capability

35. Quality of test (QOT) – Technical challenges
HIGH SPEED Interface Challenges
Korea test workshop Oct Jin-Soo Ko

36. Jedec Data

37. LPDDR3 and ddr4 specs Extremely difficult timing Accuracy Requirements
LP-DDR3 (After leveling)
LP-DDR4
Extremely difficult timing Accuracy Requirements
DDR3 Used DFT functions to validate
DDR4 may be too difficult for DFT
Might require production test with ATE to guarantee spec

38. Site-to-site Correlation problems
DDR Test Strategies
Test Strategy
ATE Solution
Pros
Cons
DUT DFT Required
Low
Cost
At-speed Test
System Level Test
Does Timing Tests
Complex DIB
Site-to-site Correlation problems
Drive / Compare Predictable data
Loopback on byte to another
Don’t Change Frequency
Keep Clock Running
Extend Latency
Loopback
DC Levels/ static Logic
Low Cost DC Option
DRAM on DIB
DRAM(s) on DIB
Internal Loopback NA ?
External Loopback
Loopback to 1100Mbps
Unclocked loopback to 2200Mbps on subset of pins
DIB Board Switching
Protocol Aware
DDR Protocol Aware
Stored Patterns
Digital pattern test with source synchronous capability
High Speed Digital Option
Very Little DFT Needed

39. High speed serial test High Speed Serial Challenges Test Strategy
ITRS Data Rate Forecast
High Speed Serial Challenges
Maintain signal integrity from Instrument to DUT
Support rapid increases in serial data rates
2013: 16Gbps
2014: 28+Gbps
2015: 45Gbps / MultiLevel
Minimize tester capital investment
Maximize tester capital useful life
Test Strategy
Support high pin count interfaces with standard tester instrument
Develop Re-useable IP than can be implemented on DIBs or DIB modules
Deliver solutions as
Turnkey applications
Vendor-designed and manufactured hardware only
Custom hardware made by ATE vendor, 3rd Party or HiSilicon (under license)
“Maintain signal integrity…”: The Viper SL is reusing the signal delivery from the PS9G and has degraded rise time, jitter and eye opening relative to the US10g and the xD modules. The fidelity is marginal or unacceptable at 12.8Gbps and is unlikely to be sufficient at 16Gbps (Viper SL version B.)
->good fidelity guarantees you’re testing the device and not the DIB
->controlled degradation of through jitter injection and low drive levels allow testing the DUT in a measurable environment.
Advantages
No need to buy new Tester Options – much lower cost
Minimizes signal path to DUT for best signal quality and device yield
Simplifies DIB by eliminating matching circuitry
Can be customized easily

40. Future standards
New PAM (Pulse Amplitude Modulation) Standard is coming
Targeted for 2015
16Gsym/s
16Gsym/s
Similar technology used on Hard Disk Drive and LAN devices
Module-Based Solution will allow a solution quickly and inexpensively

41. Towerless Probe for TSV and Bumped die
Standard Prober Docking
Towerless Prober Docking
Tester
Tester
PIB
Probe Card
Prober
Probe tower
Prober
Probe Head
Probe Card
Probe Head
Advantages:
Higher signal fidelity
Lower tooling costs
Better planarity with chuck
Standard Prober Docking
Instrument
PIB
Probe Tower
Probe Card
Probe Head
pogos
Solder pads
Probe Needles
interposer
Instrument
Probe Card
Probe Head
Solder pads
Probe Needles
Towerless Prober Docking
interposer

42. Time To Market SW and debugging tools Adaptive testing Protocol Aware
Conclusion
Cost of Test ATE Capital Program development Multisite and Concurrent test Pattern Oriented Test DFT dependent test solutions
Time To Market SW and debugging tools Adaptive testing Protocol Aware
Test Quality DC accuracy and power RF AC speed and skew High speed IO Direct Wafer Probing
Korea test workshop Oct Jin-Soo Ko

43. Q&A Q&A Jin-Soo Ko Highbrand building 10’th floor,
YangJa, SeoCho, Seoul Korea