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FUTURE IC TEST CHALLENGES QUALITY, COST AND TIME TO MARKET Korea test conference workshop 2014 Jin-Soo Ko Teradyne Inc. Korea test.

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Presentation on theme: "FUTURE IC TEST CHALLENGES QUALITY, COST AND TIME TO MARKET Korea test conference workshop 2014 Jin-Soo Ko Teradyne Inc. Korea test."— Presentation transcript:

1 FUTURE IC TEST CHALLENGES QUALITY, COST AND TIME TO MARKET Korea test conference workshop 2014 Jin-Soo Ko Teradyne Inc. Korea test workshop Oct Jin-Soo Ko

2 Fast Ramps Essentially full volume from product launch for high profile new products Must bring up new silicon process at the same time (14nm, FinFET) Yield must be good to reduce cost but defect rate must be extremely low MOBILE DEVICE CHALLENGES Number of units sold during the first weekend of product introduction COT is important but getting to market quickly with the best quality is what really counts! Silicon Samples Mass Production DaysWeeks “Zero” DPM

3 ADVANCED SILICON PROCESS AND VDD

4 Roadmap for Gate Length and Supply Voltage ITRS SEMICONDUCTOR ROADMAP

5 MARKET TRENDS DRIVING IC TEST 5 Test Fast Time To Market Less Than 15 Days Si to Samples Functional Integration Large Test Lists Collaborative Development Quality <100 DPM For Mobility Devices Complex Flows Increased Device Configuration and Repair COT Pressures Higher Multisite, Concurrent Test, Datalog overhead Faster Time To Volume > 1M devices within 2 Months

6 WHAT IS THE MOST IMPORTANT FOR TEST? (FROM ITRS) Cost of Test, Time To Market and Test Quality are equally Important Why? Test Costs are a small part of the overall cost to make an IC. Focusing only on this does not increase profit much In the mobile space, being first to market captures more market share which increases profit the most Equipment manufacturers will not accept poor IC quality. High quality devices have higher value and bring more profit. Higher yield also means lower overall cost. Korea test workshop Oct Jin-Soo Ko

7 COST OF TEST(COT) ATE Capital costs are actually decreasing This also increases Time To Market “consumable” items like probe cards and sockets are increasing in costs Cost trends (ITRS) Korea test workshop Oct Jin-Soo Ko

8 COST OF TEST(COT) Very dependent on DFT Technology Could potentially eliminate System Level Test insertion to lower costs Cost trends (ITRS) Korea test workshop Oct Jin-Soo Ko

9 DESIGN COMPLEXITY AND SCAN DEPTH Compression contained ATE memory requirements growth from 2000 to 2010, but is approaching theoretical limits Reduced Pin Count Test Will Drive Memory Requirements Higher Also puts strain on datalog and post processing features Current Industry Practice

10 As devices get more complex and scan compression can’t keep up, test times will get longer Increased ATE efficiency keeps COT flat Higher Site count (Multi-site Testing) is the most efficient way to reduce costs Similar to memory test MORE SCAN TESTING = MORE TEST TIME 3X scan test time in 5 years due to higher gate count

11 PMIC RF Tx/Rx ABB FM BT PMIC RF Tx/Rx ABB FM BT PMIC RF Tx/Rx ABB FM BT Time Concurrent PMIC BB RF FM BT USB PMIC BB RF FM BT USB *Shared device functions prevent some concurrency ~17s ~11s (estimated) COT - MULTI-SITE AND CONCURRENT TEST AND TTR => 35% TTR (estimated) Test Throughput improvement N=16 sites (PTE 0.98) 35% test time reduction by concurrent test, Multi-site test throughput0.98xN site Concurrent test throughput 1/( ) Throughput = 0.98x16/(1-0.35) = Korea test workshop Oct Jin-Soo Ko

12 CONCURRENT TEST PROGRAMMING AND DEBUG TOOL Tests Block A Tests Block B Tests Block C Tests Block D Tests Block E Initial Tests Block F Test Time Full Functional Test Concurrent Test Flow Serial Test Flow Tests Block A Tests Block B Tests Block C Tests Block D Tests Block E Tests Block F Test Time Initial Full Functional Test Development Challenges Common bus/pins Shared test resources Flow manipulation Multi-site implementation Adaptive test & Retest Debug tools Timeline viewer

13 13 Multi-site capability is the key strategy to achieve low COT 4-site codec in site CDP/DVDP in site Mobile A/V processor in site Mobile A/V processor in site Mobile Application Process in siite from 2015 ? Multi-site Test Roadmap FLEX 8-site CD, DVD Player Processor SOC test solution 16-site Mobile A/V Processor SOC test solution or 4-site 16-site 32-site 16-site UltraFLEX Catalyst/Tiger 4-site Optical Disk Drive SOC test solution 8-site 32-site Mobile A/V Processor SOC test solution UltraFLEX-HC site >1000 pin count SOC device test HIB design solution using new high density (x2 ~ x4) digital, AC, and DC options UltraFLEX-XD TIU+DSA >> 32// 2016 Korea test workshop Oct Jin-Soo Ko

14 COT - MULTI SITE COUNT TEST ROADMAP 14 “High Mix” = many different device types tested in small lots “Low Mix” = only a few device types tested in large lots Number of Sites

15 COT - MULTI SITE VS. PARALLEL TEST EFFICIENCY 15 Korea test workshop Oct Jin-Soo Ko

16 AWG SEQUENCE FOR PATTERN BASED PROGRAMMING BUCK1 BUCK2BUCK3 BUCK4 BUCK5 BUCK6 BUCK7 VIN MCU LNR1 LNR2 LDR1LDR2LDR3  The entire AWG Plots The scale reference is different in each plots. Korea test workshop Oct Jin-Soo Ko

17 COT - CHIP TO CHIP DATA Korea test workshop Oct Jin-Soo Ko

18 COT - PATTERN BASED PROGRAMMING TEST TIME  BUCK,BUCK_DVS and LDO,LDO_LDR Test time reduction ItemsBefore[mS]After[mS]TTR[%] BUCK BUCK_DVS LDO_LDR LDO Total Korea test workshop Oct Jin-Soo Ko

19 COT - UPGRADE TEST COMPUTER Next generation tester computer Load & Validate time improvement up to ~ 20% Average Runtime Improvement of ~ 4% to 20% Windows 7 33% increase in application memory Microsoft Office 2010 Interoperability between Excel 2010 and Excel 2003 New Sheet-Grouping and Navigation Features Benchmark Test Summary: Tera1 Windows7 Benchmark Test Summary: Tera1 Windows7 Market SegmentRun Time PMIC4.75% MAP+ DBB4.30% Connectivity5% CODEC11% Cellular20%

20 COT – BUY RATE DOWN EQUIPMENT CAPITAL BUY RATE DOWN Test equipment is already very efficient. Most new “test” investment focused on Time To Market and Quality to improve IC revenue and market share “Buy Rate” = ATE Cost / IC Revenue 1% 2013 $1.00 of IC revenue = $0.005 of test capital Lowering Cost of Test 10% only increases profit by 0.05% Raising Yield from 95% to 96% increases profit by > 1% (Much better investment!) Winning new socket increases market share (Best investment!) Buy Rate “Front End” Costs “Back End” Costs Korea test workshop Oct Jin-Soo Ko

21 TIME TO MARKET (TTM) What is this and why you should care? Directly impact to market share and profits Smart phone market is never wait for the delay of test. Korea test workshop Oct Jin-Soo Ko

22 TTM - HOW TO GET FAST TIME TO MARKET ? Industry standard test system and SW capability Integration with design and bench test Advanced ATE SW tools for Time to Market EDA Systems ATPG Tools Adaptive Test Real-time Fault Isolation Physical Failure Analysis “Big Data” Storage DesignSimulation On-Tester Debug/ Characterization (hours/minutes) Timing/Levels Mixed Signal Repeatability Correlation Pattern & Test program. Gen. events transactions ATPG STDF “off tester” tools “on tester” tools Failure Analysis / Yield Enhancement EDA-based Pattern Viewer Simultaneous display of EDA and tester information Diagnose Physical Device Faults EDA-based Pattern Viewer Simultaneous display of EDA and tester information Diagnose Physical Device Faults Design  Test  Design Loop Korea test workshop Oct Jin-Soo Ko

23 TTM - MULTI-SHEET USE MODEL Separate test code & data for each sub program Tied together at the Job List Sheet Multi-Sheet Model Sub-Program B Sub-Program A Enabler for independent development Reduces time to integrate = no more manual merging of sub programs

24 TTM - RF TOOLS- LTE-A TX SIGNAL DEBUG TOOL IG-XL 7.30 ESA 2.0 3GPP LTE TD-SCDMA n 4x4 MIMO VSA port vector Power de-embedding Signal sheet support Smith charting IG-XL 7.40 ESA 2.5 3GPP LTE Update Bluetooth 3.0 VSA 11 IG-XL ESA 3.0 LTE 8.9 VSA12 IG-XL 8.10 ESA 3.5 LTE-A (R10) ac VSA 14 IG-XL 8.20 ESA 4.0 LTE-A (100MHz) ac (160MHz) ac (80+80) BT 4.0 (LE) VSA 16 90% reduction in VSA instance creation times Korea test workshop Oct Jin-Soo Ko

25 Match an independent part of the tester to each interface Match the device’s frequency, timing, etc. Communicate natively in the “Language” of the port Integrated Mobile Device CPU Mem I/F Mem I/F DRAM Emulation Engine JTAG Protocol Engine JTAG I/F USB I/F USB Protocol Engine DSP BB Proc Power Mgmt Functions DC Test Resources Audio / BB Functions AC Test Resources GPS 4G WiFi FM/TV Modulation Domain RF Protocol Level ATE Protocol Synchronization & Communication TTM - How To Do Protocol Level Test?

26 “Stored Response” ATE Complex Device Architecture Tries to Test Integrated Mobile Device CPU DRAM I/F DRAM I/F Flash I/F Flash I/F JTAG I/F JTAG I/F USB I/F USB I/F DSP BB Proc BB Proc Power Mgmt Functions Power Mgmt Functions Audio / BB Functions Audio / BB Functions GPS 3G RF WiFi FM/TV Write.jtag ( ADDR: 04h, DATA: 55h) Read.jtag (ADDR: 0Ah, DATA  read_var) Protocol Definition Editor For defining and modifying protocols Protocol Studio For online debug of protocol transactions Transaction results Debug displaysData capture setups Module managementPort Properties TTM - PROTOCOL AWARE

27 DEVICE TRENDS DRIVE NEW TEST NEEDS Lithography More scan testing with failure capture and diagnosis capability = More Patterns, especially at the start of the product life Need to capture high volumes of scan data for offline analysis Higher speed Data IO High Speed Characterization capability with phenomenal Timing accuracy. Ability to use higher performance standard digital to screen devices in production to augment DFT. DFT- Only approach has more risk as data rates increase. Lower voltage Device Supplies < 700mV require excellent accuracy. Huge Current steps cannot cause glitches More complex RF Standards Precise measurement of complex RF constellations Larger number of RF measurements Device Re- configuration More Complex Test Programs to do different testing per site New Packaging Ability to do a complete test at probe System Level Test capability for stacked die Mapping Physical and electrical defects Power Supply Stability Example Test Flow Site 1Site 2 QUALITY OF TEST (QOT) – TECHNICAL CHALLENGES

28 Korea test workshop Oct Jin-Soo Ko DC CHALLENGES

29 Supply Voltage levels will continue to decrease New test requirements for power supplies to be stable and accurate Need very critical DIB PI simulation and design process QOT - ITRS SEMICONDUCTOR ROADMAP FOR GATE LENGTH AND SUPPLY VOLTAGE

30 AP requires many supplies Core supplies IO Supplies Requirements are very different Core: Accuracy, dynamic performance IO: Wider voltage range, more connections TEST QUALITY - DC POWER VDD ACCURACY & DROOP All device supplies will have some momentary “droop” when scan patterns are started. Too large a “droop” will cause good parts to fail, reducing yield Power Supply Stability Example Single Supply Solution Ganged Solution Network Processor Example

31 QUALITY OF TEST (QOT) – TECHNICAL CHALLENGES Korea test workshop Oct Jin-Soo Ko RF CHALLENGES

32 Increase Demand for Higher Data Rate & Connectivity Overall mobile data traffic is expected to grow at a 61% CAGR to 15.9 Exabytes per month by 2018 Migration to LTE-Advanced occurring in all market segment (high and low end) New standards require 2x-3x more active RF device ports Demand for higher performance and high site count test capability Internet-of-things driving rapid growth of MCU + RF segment Shrinking Device Size While Increasing Complexity Mobile IC’s moving away from conventional package to wafer-level package technologies (Flip-chip, WLCSP, FOWLP) WIRELESS INDUSTRY TRENDS

33 LTE TEST CHALLENGES – MODULATION QUALITY When Testing an RF Device, we want to measure how much the signal is corrupted by things like: Phase Noise Signal Imbalance Other noise and distortion All of these errors are combined into Error Vector Magnitude. It is a clear way to measure RF signal quality To do production testing, the EVM of the tester must be much better than the Device Under Test When Testing an RF Device, we want to measure how much the signal is corrupted by things like: Phase Noise Signal Imbalance Other noise and distortion All of these errors are combined into Error Vector Magnitude. It is a clear way to measure RF signal quality To do production testing, the EVM of the tester must be much better than the Device Under Test Ideal Signal Measured Signal Test Limit LTE Base Station = 13.5% LTE User Equip 12.5% ac = 11.22% LTE Base Station = 9.0% ac = 3.98% ac = 2.51% 16-QAM a/g, LTE 64-QAM a/g/n; LTE-A 256-QAM ac - Device Spec Limit

34 802.11ac 160M EVM Limit = 2.51% The plot below shows the effects of IQ skew Imbalances (modulation signals being out of phase) If testing an actual device, the skew, gain and other distortion would contribute to the EVM error. EXAMPLE OF HOW TESTER ERRORS BECOME MORE CRITICAL FOR NEW RF STANDARDS LTE 20M LTE-A 100M Skew Tester with 1-2% EVM Test Capability ac 160M Tester with 0.5% EVM Test Capability Can’t Test! X Good Test Margin

35 QUALITY OF TEST (QOT) – TECHNICAL CHALLENGES Korea test workshop Oct Jin-Soo Ko HIGH SPEED INTERFACE CHALLENGES

36 JEDEC DATA

37 Extremely difficult timing Accuracy Requirements DDR3 Used DFT functions to validate DDR4 may be too difficult for DFT Might require production test with ATE to guarantee spec LPDDR3 AND DDR4 SPECS LP-DDR3 (After leveling) LP-DDR4

38 DDR TEST STRATEGIES Test Strategy ATE Solution ProsCons DUT DFT Required Low Cost At-speed Test System Level Test Does Timing Tests Complex DIB Site-to-site Correlation problems Drive / Compare Predictable data Loopback on byte to another Don’t Change Frequency Keep Clock Running Extend Latency Loopback DC Levels/ static Logic Low Cost DC Option DRAM on DIBDRAM(s) on DIB Internal Loopback NA ? External Loopback Loopback to 1100Mbps Unclocked loopback to 2200Mbps on subset of pins DIB Board Switching Protocol AwareDDR Protocol Aware Stored Patterns Digital pattern test with source synchronous capability High Speed Digital Option Very Little DFT Needed

39 High Speed Serial Challenges Maintain signal integrity from Instrument to DUT Support rapid increases in serial data rates 2013: 16Gbps 2014: 28+Gbps 2015: 45Gbps / MultiLevel Minimize tester capital investment Maximize tester capital useful life Test Strategy Support high pin count interfaces with standard tester instrument Develop Re-useable IP than can be implemented on DIBs or DIB modules Deliver solutions as Turnkey applications Vendor-designed and manufactured hardware only Custom hardware made by ATE vendor, 3 rd Party or HiSilicon (under license) HIGH SPEED SERIAL TEST Advantages No need to buy new Tester Options – much lower cost Minimizes signal path to DUT for best signal quality and device yield Simplifies DIB by eliminating matching circuitry Can be customized easily Advantages No need to buy new Tester Options – much lower cost Minimizes signal path to DUT for best signal quality and device yield Simplifies DIB by eliminating matching circuitry Can be customized easily ITRS Data Rate Forecast

40 New PAM (Pulse Amplitude Modulation) Standard is coming Targeted for Gsym/s 16Gsym/s Similar technology used on Hard Disk Drive and LAN devices Module-Based Solution will allow a solution quickly and inexpensively FUTURE STANDARDS 40

41 TOWERLESS PROBE FOR TSV AND BUMPED DIE Probe Card PIB Probe tower Standard Prober Docking Towerless Prober Docking Tester Probe Card Standard Prober Docking InstrumentPIB Probe Tower Probe Card Probe Head pogos Solder padsProbe Needles interposer Instrument Probe Card Probe Head Solder padsProbe Needles Towerless Prober Docking interposer Probe Head Advantages: -Higher signal fidelity -Lower tooling costs -Better planarity with chuck Advantages: -Higher signal fidelity -Lower tooling costs -Better planarity with chuck Tester

42 CONCLUSION Cost of Test ATE Capital Program development Multisite and Concurrent test Pattern Oriented Test DFT dependent test solutions Time To Market SW and debugging tools Adaptive testing Protocol Aware Test Quality DC accuracy and power RF AC speed and skew High speed IO Direct Wafer Probing Korea test workshop Oct Jin-Soo Ko

43 Q&A Jin-Soo Ko Highbrand building 10’th floor, YangJa, SeoCho, Seoul Korea


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