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Korea Test Conference Jin-Soo Ko June 25, 2014 ATE Debugging tool 효율적 테스트 / 디버그를 위한 디자인과 테스트 업체의 연구 방안.

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Presentation on theme: "Korea Test Conference Jin-Soo Ko June 25, 2014 ATE Debugging tool 효율적 테스트 / 디버그를 위한 디자인과 테스트 업체의 연구 방안."— Presentation transcript:

1 Korea Test Conference Jin-Soo Ko (jin-soo.ko@teradyne.com) June 25, 2014 ATE Debugging tool 효율적 테스트 / 디버그를 위한 디자인과 테스트 업체의 연구 방안

2 SW AND DEBUG TOOLS MAGNIFY NEEDLE!

3 MARKET TRENDS DRIVING ATE SW TOOL ROADMAP 3 Test Engineer Shorter Time To Market Less Than 15 Days Si to Samples Functional Integration Large Test Lists Collaborative Development Quality <100 DPM For Mobility Devices Complex Flows Increased Device Configuration and Repair COT Pressures Higher Multisite, Concurrent Test, Datalog overhead Faster Time To Volume > 1M devices within 2 Months

4 IG-XL: #1 IN ATE SOFTWARE - WHY NEED GOOD SW-DEBUG TOOL? 30% faster test program development time Native MultiSite, Program Modularity, Templates, “Debug in the Zone”, Complete tool set, ESA Optimal throughput early in the product ramp resulting in faster time to profits. IG-XL’s Pure Parallel, Native MultiSite, Background DSP, TrueCT, Timelines Faster time to entitled yield Scan fail capture throughput, APIs to design environments, Protocol Aware Better quality programs that result in fewer RMAs and defect escapes VBT, Spike-Check tool, Simulation Tools, IG-Review, IG-Diff New users become self sufficient faster Easy to learn programming language, DUT Centric use model, Template programming IG-XL has been ranked #1 in ATE Software for the last four years by VLSI Customer Satisfaction Research Survey

5 DESIGN  TEST  DESIGN LOOP DesignSimulation On-Tester Debug/ Characterization (hours/minutes) Timing/Levels Mixed Signal Repeatability Correlation Pattern & Test program. Gen. events transactions ATPG STDF “off tester” tools “on tester” tools Failure Analysis / Yield Enhancement EDA-based Pattern Viewer Simultaneous display of EDA and tester information Diagnose Physical Device Faults EDA-based Pattern Viewer Simultaneous display of EDA and tester information Diagnose Physical Device Faults 5

6 HOW ARE SCAN FAILURES RESOLVED NOW? Tools are not integrated Information is lost or delayed between Test / Design / FA Investigations can take weeks to complete 6

7 Teradyne Confidential THE TESTER IS ONLY PART OF A BIGGER PROCESS Advanced ATE SW tools for Time to Market

8 OPENEDA: CONNECTING ATE SW (IG-XL) TO THE ENTIRE DESIGN AND TEST ENVIRONMENT Design and Test Development: EDA Links Test Program Generation Feedback To Simulation Test-Design Integration Yield Learning Data Analysis High Volume Manufacturing: Test Floor Management Factory Data Management Adaptive Test Part Average Testing Operator Interfaces Peripherals and Handlers Yield Monitoring OEE 8

9 Program Instruments with Psets (All instruments in parallel) Select Source Signal Trigger measurements at precise times Reprogram Instruments with PSets Select different Source Signal Trigger measurements at precise times Automatic data move and processing -3dB Automatic data move and processing …and so on… Since the Engineer can control all the events from one pattern, we have Pattern Oriented Programming (POP) Exact Timeline WHAT THE TEST ENGINEER SEES…. POP 9

10 CONCURRENT TEST TOOL Tests Block A Tests Block B Tests Block C Tests Block D Tests Block E Initial Tests Block F Test Time Full Functional Test Concurrent Test Flow Serial Test Flow Tests Block A Tests Block B Tests Block C Tests Block D Tests Block E Tests Block F Test Time Initial Full Functional Test Development Challenges Common bus/pins Shared test resources Flow manipulation Multi-site implementation Adaptive test & Retest Debug tools 10 Timeline viewer

11 MULTI-SHEET USE MODEL Separate test code & data for each sub program Tied together at the Job List Sheet IG-XL 8.10.11 completes the Multi-Sheet Model Sub-Program B Sub-Program A Enabler for independent development Reduces time to integrate = no more manual merging of sub programs

12 RF TOOLS- LTE-A TX SIGNAL DEBUG TOOL AND RESULT IG-XL 7.30 ESA 2.0 3GPP LTE TD-SCDMA 802.11n 4x4 MIMO VSA 10.01 1 port vector Power de-embedding Signal sheet support Smith charting IG-XL 7.40 ESA 2.5 3GPP LTE Update Bluetooth 3.0 VSA 11 IG-XL 8.00.01 ESA 3.0 LTE 8.9 VSA12 IG-XL 8.10 ESA 3.5 LTE-A (R10) 802.11ac VSA 14 IG-XL 8.20 ESA 4.0 LTE-A (100MHz) 802.11ac (160MHz) 802.11ac (80+80) BT 4.0 (LE) VSA 16 90% reduction in VSA instance creation times

13 PROTOCOL AWARE “Stored Response” ATE Complex Device Architecture Tries to Test Integrated Mobile Device CPU DRAM I/F DRAM I/F Flash I/F Flash I/F JTAG I/F JTAG I/F USB I/F USB I/F DSP BB Proc BB Proc Power Mgmt Functions Power Mgmt Functions Audio / BB Functions Audio / BB Functions GPS 3G RF WiFi FM/TV Write.jtag ( ADDR: 04h, DATA: 55h) Read.jtag (ADDR: 0Ah, DATA  read_var) Protocol Definition Editor For defining and modifying protocols Protocol Studio For online debug of protocol transactions Transaction results Debug displays Data capture setups Module management Port Properties


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