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1 of 24 The new way for FPGA & ASIC development © 2004-2007 GE-Research.

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Presentation on theme: "1 of 24 The new way for FPGA & ASIC development © 2004-2007 GE-Research."— Presentation transcript:

1 1 of 24 The new way for FPGA & ASIC development © GE-Research

2 Semulator V2.2dsr2 of 24 Development of complex FPGA and ASIC Stable parts transferred to Hpe_midi Design File VHDL Design File Verilog Testbench Files HDL Simulator and Hpe Desk Design File SystemC Design FilesMacro3Macro4Macro1Macro2 Simulation & Emulation Stable parts transferred to Hpe_midi SEmulation = Simulator controlled Emulation Hpe_midi R a p i d P r o t o t y p i n g S y s t e m H D L S i m u l a t o r

3 Semulator V2.2dsr3 of 24 Development of complex FPGA and ASIC Testbench Files HDL Simulator and Hpe Desk Macro3Macro4 Hpe_midi Design File VHDL Macro1Macro2 Switch off a FPGA block bug challenge specification change Simulate with a new model Macro3 disabled Macro3A Design finished! H D L S i m u l a t o r R a p i d P r o t o t y p i n g S y s t e m

4 Semulator V2.2dsr4 of 24 Wave Window Development of complex FPGA and ASIC debugging Testbench HDL Simulator and Hpe Desk Hpe_midi H D L S i m u l a t o r R a p i d P r o t o t y p i n g S y s t e m PCIeX4 over Cable debugging on hardware with trusted test bench + hardware assertions (simple subset of PSL)

5 Semulator V2.2dsr5 of 24 Hardware in the Loop Hpe_midi Macro1 Macro n... Ext. Component e.g. CPU Hpe_child board Standard components can be implemented directly into simulation and emulation Testbench Files HDL Simulator and Hpe Desk Design File VHDL H D L S i m u l a t o r R a p i d P r o t o t y p i n g S y s t e m Used for EmulationUsed for Simulation Controlled by a click in Hpe_desk

6 Semulator V2.2dsr6 of 24 Clock Acceleration* Testbench Files HDL Simulator and Hpe Desk Macro3Macro4 Hpe_midi Macro1Macro2 Controlled by user Clock Factory up to 100 MHz Simulator clock 20kHz – 200 kHz *International patent applied Individual clock for every macro Runs your Modelsim ® simulation in “real time” H D L S i m u l a t o r R a p i d P r o t o t y p i n g S y s t e m

7 Semulator V2.2dsr7 of 24 What you need for SEmulation: A standard FPGA development system e.g. Hpe_midi A PCIe X4 over cable communication card e.g. Hpe_com1 Software package Hpe_desk includes SEmulator, Clock Factory Programmer, JTAG Scanner/Debugger, ALTERA Quartus And last but not least a PC and MENTOR Modelsim

8 Semulator V2.2dsr8 of 24 Faster Simulation The SEmulator can speed up your Modelsim simulation:

9 Semulator V2.2dsr9 of 24 Clock Factory You can program every clock source -> clock input by a click

10 Semulator V2.2dsr10 of 24 JTAG Debugger / Scanner You can read and write every pin of every component in the JTAG chain, customer specific chain in DUT is supported.

11 Semulator V2.2dsr11 of 24 Advantages of SEmulation Early and continued testing of final hardware  Higher design quality / reliability Dramatically decrease RTL simulation time  Decrease development time Standard FPGA board for development, different boards available  No additional hardware cost Hardware in the Loop (Cosimulation)  Every external hardware can be implemented easily in the SEmulator ‘No’ limitation on pin and gate count  Broad family concept – Many extension boards

12 Semulator V2.2dsr12 of 24 What are successful teams doing? Collett International Research Inc., 2004 IC/ASIC Functional Verification Study

13 Semulator V2.2dsr13 of 24 H u m a n I n t e r f a c e Internal and external LCD Connector Keyboard DIPLED FPGA Prototyping Area Clock Factory Reset Power Supply 3,3V 2,5V 12V Hpe_child Connector Hpe_child Connector Santa Cruz Connector USB2.0 FS-Host USB2.0 FS-Host USB2.0 FS-OTG Ethernet 10/100 RS232 LINCAN VGA 3 * 8bit PS2AC97 SD-Card FLASH 8M*32 SRAM 256k*32 EEPROM 2k bit 720 pin Hpe Module Connector 473 I/O plus Power Supply 6-12 bit D/A 6-12 bit A/D USB2.0 HS-Target Motherboard for FPGA development

14 Semulator V2.2dsr14 of 24 The Enclosure - Protect your hardware

15 Semulator V2.2dsr15 of 24 1 FPGA module for FPGA development with or without SEmulation ( ) Logic Elements = 1.8 (3,4) Mio ASIC gates *) Hardware in the Loop Every Child Board can be used for simulation and for emulation *) Figures in brackets are STRATIX3 values I/O manager can be added on request Clock Factory IP & SW Protection Controller Hpe_module1X Child Board High speed access L4 Hpe_module connector 473 I/O plus power supply Child Board EP2S180 DUT Common Config. Device ALTERA USB Blaster To PC Communication Controller PCIe X4 over cable Hpe_PCIe Child Board

16 Semulator V2.2dsr16 of 24 Child Board 2 FPGA module for FPGA development with or without SEmulation ( ) Logic Elements = 3.6 (6.8) Mio ASIC gates High speed access 2 * L4 Hpe_module connector 473 I/O plus power supply EP2S180 DUT Child Board EP2S180 DUT 512 single ended bus 128 LVDS pairs between every FPGA Common Config. Device ALTERA USB Blaster Clock Factory To PC IP & SW Protection Controller Hpe_module2X Communication Controller PCIe X4 over cable Hpe_PCIe Child Board

17 Semulator V2.2dsr17 of 24 4 FPGA module for FPGA development with or without SEmulation 720k (1,3 Mio) Logic Elements = 7,2 (13) Mio ASIC gates Common Config. Device ALTERA USB Blaster Clock Factory To PC IP & SW Protection Controller PCIe X4 over cable Communication Controller Hpe_PCIe Child Board 256 bit single ended bus 64 LVDS pairs between every FPGA high speed access (L4) EP2S180 DUT EP2S180 DUT EP2S180 DUT EP2S60 Board Controller Child Board o 48 LVDS-I/O u 128 se EP2S180 DUT Child Board o L17 u L17 u L16 Child Board o 48 LVDS-I/O u 128 se Child Board o 48 LVDS-I u 128 se Child Board o 48 LVDS-O u 128 se Child Board o L17 Child Board o 128 se Child Board o 128 se Child Board o 128 se Child Board o 128 se DDR2 socket Hpe_module4X

18 Semulator V2.2dsr18 of 24 Common Config. Device ALTERA USB Blaster Clock Factory To PC IP & SW Protection Controller PCIe X4 over cable Communication Controller Hpe_PCIe Child Board ModuleX4 Mainboard Hpe_childboard 1,6M (3 Mio) Logic Elements = 16 (30) Mio ASIC gates high speed access EP2S180 DUT EP2S180 DUT EP2S180 DUT EP2S60 Board Controller Child Board o 48 LVDS u 64 LVDS EP2S180 DUT Child Board o 2 * L16 u 2 * L16 u L16 Child Board o 48 LVDS u 64 LVDS Child Board o 48 LVDS u 64 LVDS Child Board o 48 LVDS u 64 LVDS Child Board o L16 Child Board o 64 LVDS Child Board o 64 LVDS Child Board o 64 LVDS Child Board o 64 LVDS DDR2 socket high speed access EP2S180 DUT EP2S180 DUT EP2S180 DUT EP2S60 Board Controller Child Board o 48 LVDS u 64 LVDS EP2S180 DUT Child Board o 2 * L16 u 2 * L16 u L16 Child Board o 48 LVDS u 64 LVDS Child Board o 48 LVDS u 64 LVDS Child Board o 48 LVDS u 64 LVDS Child Board o L16 Child Board o 64 LVDS Child Board o 64 LVDS Child Board o 64 LVDS Child Board o 64 LVDS DDR2 socket Hpe_module8X

19 Semulator V2.2dsr19 of 24 Hpe_child Board Hpe_child board with 99 I/O signals Easy stackable, easy connectable to Logic Analyzer Connects the SEmulator with the ‚real world‘ Development plan for 2006/2007 –Universal connector and test board –DDR1 and DDR2 RAM –1G Ethernet (twice) –A/D and D/A for high speed –A/D and D/A for high resolution –Video in and Video out –8 UART / RS232 –MOST and FlexRay –Wireless (Nanonet and/or Bluetooth) –High speed optical –PCI Express external X4 and X8(16) We develop customer specific child boards on demand (Ask for details of our development participation program) Hpe_child board connector: 130 pin, 99 usable I/O Example of a Hpe_child board Adapter board to connect a logic analyzer

20 20 of 24 C o n f i d e n t i a l The next Generation

21 21 of 24Semulator V2.2dsr 4 FPGA module for FPGA development with or without SEmulation 720k (1,3 Mio) Logic Elements = 7,2 (13) Mio ASIC gates Common Config. Device ALTERA USB Blaster Clock Factory To PC IP & SW Protection Controller PCIe X4 over cable Communication Controller Hpe_PCIe Child Board high speed access EP2S180 DUT EP2S180 DUT EP2S180 DUT EP2S60 Board Controller Child Board o 48 LVDS u 64 LVDS EP2S180 DUT Child Board o 2 * L16 u 2 * L16 u L16 Child Board o 48 LVDS u 64 LVDS Child Board o 48 LVDS u 64 LVDS Child Board o 48 LVDS u 64 LVDS Child Board o L16 Child Board o 64 LVDS Child Board o 64 LVDS Child Board o 64 LVDS Child Board o 64 LVDS DDR2 socket Hpe_module4XL C o n f i d e n t i a l

22 22 of 24Semulator V2.2dsr 2 FPGA module for FPGA development with or without SEmulation PCIe X4 over cable Communication Controller Hpe_PCIe Child Board Common Config. Device ALTERA USB Blaster Clock Factory To PC IP & SW Protection Controller high speed access EP2S180 DUT Child Board o 48 LVDS u 64 LVDS EP2S180 DUT Child Board L4 o L4 u L16 Child Board o 48 LVDS u 64 LVDS Child Board o 64 LVDS Child Board o 64 LVDS DDR2 socket Hpe_module2XL C o n f i d e n t i a l

23 23 of 24Semulator V2.2dsr 1 FPGA module for FPGA development with or without SEmulation PCIe X4 over cable Communication Controller Hpe_PCIe Child Board Common Config. Device ALTERA USB Blaster Clock Factory To PC IP & SW Protection Controller high speed access EP2S180 DUT Child Board o 48 LVDS u 64 LVDS Child Board o L 4 u L16 Child Board o 48 LVDS u 64 LVDS Child Board o 64 LVDS Child Board o 64 LVDS DDR2 socket Hpe_module1XL C o n f i d e n t i a l

24 24 of 24Semulator V2.2dsr H u m a n I n t e r f a c e on front panel 4 * 20 char LCD Keyboard DIPLED Clock Factory Reset Power Supply 3,3V 2,5V 12V USB2.0 FS-Host USB2.0 FS-Host USB2.0 FS-OTG Ethernet 10/100 RS232 LINCAN VGA 3 * 8bit PS2AC97 SD-Card Motherboard for FPGA development 6-12 bit D/A 6-12 bit A/D USB2.0 HS-Target Modul Connector 128 I/O pin FLASH 8M*32 SRAM 256k*32 Modul Connector 128 I/O pin Modul Connector 128 I/O pin SDRAM socket Modul Connector 128 I/O pin C o n f i d e n t i a l


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