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Prof. V.G. OklobdzijaVLSI Arithmetic1 VLSI Arithmetic Adders & Multipliers Prof. Vojin G. Oklobdzija University of California http://www.ece.ucdavis.edu/acsel

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Prof. V.G. OklobdzijaVLSI Arithmetic2 Introduction Digital Computer Arithmetic belongs to Computer Architecture, however, it is also an aspect of logic design The objective of Computer Arithmetic is to develop appropriate algorithms that are utilizing available hardware in the most efficient way. Ultimately, speed, power and chip area are the most often used measures, making a strong link between the algorithms and technology of implementation.

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Prof. V.G. OklobdzijaVLSI Arithmetic3 Basic Operations Addition Multiplication Multiply-Add Division Evaluation of Functions

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Prof. V.G. OklobdzijaVLSI Arithmetic4 Addition of Binary Numbers Full Adder. The full adder is the fundamental building block of most arithmetic circuits: The sum and carry outputs are described as: Full Adder C in C out sisi aiai bibi

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Prof. V.G. OklobdzijaVLSI Arithmetic5 Addition of Binary Numbers Propagate Generate InputsOutputs cici aiai bibi sisi c i+1 00000 00110 01010 01101 10010 10101 11001 11111

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Prof. V.G. OklobdzijaVLSI Arithmetic6 Full-Adder Implementation Full Adder operations is defined by equations: One-bit adder could be implemented as shown Carry-Propagate: and Carry-Generate g i

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Prof. V.G. OklobdzijaVLSI Arithmetic7 High-Speed Addition One-bit adder could be implemented more efficiently because MUX is faster

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Prof. V.G. OklobdzijaVLSI Arithmetic8 The Ripple-Carry Adder

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Prof. V.G. OklobdzijaVLSI Arithmetic9 The Ripple-Carry Adder From Rabaey

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Prof. V.G. OklobdzijaVLSI Arithmetic10 Inversion Property From Rabaey

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Prof. V.G. OklobdzijaVLSI Arithmetic11 Minimize Critical Path by Reducing Inverting Stages From Rabaey

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Prof. V.G. OklobdzijaVLSI Arithmetic12 Manchester Carry-Chain Realization of the Carry Path Simple and very popular scheme for implementation of carry signal path

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Prof. V.G. OklobdzijaVLSI Arithmetic13 Manchester Carry Chain Kilburn, et al, IEE Proc, 1959. Implement P with pass-transistors Implement G with pull-up, kill (delete) with pull-down Use dynamic logic to reduce the complexity and speed up

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Prof. V.G. OklobdzijaVLSI Arithmetic14 Ripple Carry Adder Carry-Chain of an RCA implemented using multiplexer from the standard cell library: Critical Path Oklobdzija, ISCAS’88

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Prof. V.G. OklobdzijaVLSI Arithmetic15 Pass-Transistor Realization in DPL

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Prof. V.G. OklobdzijaVLSI Arithmetic16 Carry-Skip Adder MacSorley, Proc IRE 1/61 Lehman, Burla, IRE Trans on Comp, 12/61

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Prof. V.G. OklobdzijaVLSI Arithmetic17 Carry-Skip Adder Bypass From Rabaey

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Prof. V.G. OklobdzijaVLSI Arithmetic18 Carry-Skip Adder: N-bits, k-bits/group, r=N/k groups

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Prof. V.G. OklobdzijaVLSI Arithmetic19 Carry-Skip Adder k

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Prof. V.G. OklobdzijaVLSI Arithmetic20 Variable Block Adder (Oklobdzija, Barnes: IBM 1985)

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Prof. V.G. OklobdzijaVLSI Arithmetic21 Carry-chain of a 32-bit Variable Block Adder (Oklobdzija, Barnes: IBM 1985)

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Prof. V.G. OklobdzijaVLSI Arithmetic22 Carry-chain of a 32-bit Variable Block Adder (Oklobdzija, Barnes: IBM 1985) 1 1 2 2 3 3 4 4 5 5 6 =9 Any-point-to-any-point delay = 9 as compared to 12 for CSKA

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Prof. V.G. OklobdzijaVLSI Arithmetic23 Carry-chain block size determination for a 32-bit Variable Block Adder (Oklobdzija, Barnes: IBM 1985)

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Prof. V.G. OklobdzijaVLSI Arithmetic24 Delay Calculation for Variable Block Adder (Oklobdzija, Barnes: IBM 1985) Delay model:

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Prof. V.G. OklobdzijaVLSI Arithmetic25 Variable Block Adder (Oklobdzija, Barnes: IBM 1985) Variable Group Length Oklobdzija, Barnes, Arith’85

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Prof. V.G. OklobdzijaVLSI Arithmetic26 Carry-chain of a 32-bit Variable Block Adder (Oklobdzija, Barnes: IBM 1985) Variable Block Lengths No closed form solution for delay It is a dynamic programming problem

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Prof. V.G. OklobdzijaVLSI Arithmetic27 Delay Comparison: Variable Block Adder (Oklobdzija, Barnes: IBM 1985)

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Prof. V.G. OklobdzijaVLSI Arithmetic28 Delay Comparison: Variable Block Adder VBA- Multi-Level CLA VBA

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Prof. V.G. OklobdzijaVLSI Arithmetic29 Fan-Out Dependency

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Prof. V.G. OklobdzijaVLSI Arithmetic30 Fan-In Dependency

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Prof. V.G. OklobdzijaVLSI Arithmetic31 Delay Comparison: Variable Block Adder (Oklobdzija, Barnes: IBM 1985)

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Prof. V.G. OklobdzijaVLSI Arithmetic32

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Prof. V.G. OklobdzijaVLSI Arithmetic33 Carry-Lookahead Adder (Weinberger and Smith) Weinberger and J. L. Smith, “A Logic for High-Speed Addition”, National Bureau of Standards, Circ. 591, p.3-12, 1958.

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Prof. V.G. OklobdzijaVLSI Arithmetic34 Carry-Lookahead Adder (Weinberger and Smith)

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Prof. V.G. OklobdzijaVLSI Arithmetic35 Carry-Lookahead Adder One gate delay to calculate p, g One to calculate P and two for G Three gate delays To calculate C 4(j+1) Compare that to 8 in RCA !

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Prof. V.G. OklobdzijaVLSI Arithmetic36 Carry-Lookahead Adder (Weinberger and Smith) Additional two gate delays C 16 will take a total of 5 vs. 32 for RCA !

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Prof. V.G. OklobdzijaVLSI Arithmetic37 32-bit Carry Lookahead Adder

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Prof. V.G. OklobdzijaVLSI Arithmetic38 Carry-Lookahead Adder (Weinberger and Smith: original derivation )

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Prof. V.G. OklobdzijaVLSI Arithmetic39 Carry-Lookahead Adder (Weinberger and Smith: original derivation )

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Prof. V.G. OklobdzijaVLSI Arithmetic40 Carry-Lookahead Adder (Weinberger and Smith) please notice the similarity with Parallel-Prefix Adders !

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Prof. V.G. OklobdzijaVLSI Arithmetic41 Carry-Lookahead Adder (Weinberger and Smith) please notice the similarity with Parallel-Prefix Adders !

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Prof. V.G. OklobdzijaVLSI Arithmetic42 Delay Optimized CLA B. Lee, V. G. Oklobdzija Journal of VLSI Signal Processing, Vol.3, No.4, October 1991

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Prof. V.G. OklobdzijaVLSI Arithmetic43 Delay Optimized CLA: Lee-Oklobdzija ‘91 (a.) Fixed groups and levels (b.) variable-sized groups, fixed levels (c.) variable-sized groups and fixed levels (d.) variable-sized groups and levels

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Prof. V.G. OklobdzijaVLSI Arithmetic44 Two-Levels of Logic Implementation of the Carry Block

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Prof. V.G. OklobdzijaVLSI Arithmetic45 Two-Levels of Logic Implementation of the Carry-Lookahead Block

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Prof. V.G. OklobdzijaVLSI Arithmetic46 Three-Levels of Logic Implementation of the Carry Block (restricted fan-in)

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Prof. V.G. OklobdzijaVLSI Arithmetic47 Three-Levels of Logic Implementation of the Carry Lookahead (restricted fan-in)

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Prof. V.G. OklobdzijaVLSI Arithmetic48 Delay Optimized CLA: Lee-Oklobdzija ‘91 Delay: Two-level BCLA Delay: Three-level BCLA

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Prof. V.G. OklobdzijaVLSI Arithmetic49 Delay Optimized CLA: Lee-Oklobdzija ‘91 (a.) 2-level BCLA =8.5nS (b.) 3-level BCLA =8.9nS

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Prof. V.G. OklobdzijaVLSI Arithmetic50 Motorola: CLA Implementation Example A. Naini, D. Bearden and W. Anderson, “A 4.5nS 96b CMOS Adder Design”, Proceedings of the IEEE Custom Integrated Circuits Conference, May 3-6, 1992.

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Prof. V.G. OklobdzijaVLSI Arithmetic51 Critical path in Motorola's 64-bit CLA

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Prof. V.G. OklobdzijaVLSI Arithmetic52 Motorola's 64-bit CLA conventional PG Block

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Prof. V.G. OklobdzijaVLSI Arithmetic53 Motorola's 64-bit CLA Modified PG Block Intermediate propagate signals P i:0 are generated to speed-up C 3

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Prof. V.G. OklobdzijaVLSI Arithmetic54 Ling’s Adder Huey Ling, “High-Speed Binary Adder” IBM Journal of Research and Development, Vol.5, No.3, 1981.

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Prof. V.G. OklobdzijaVLSI Arithmetic55 Ling Adder Variation of CLA: Ling, IBM J. Res. Dev, 5/81 Ling’s equations:

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Prof. V.G. OklobdzijaVLSI Arithmetic56 Ling Adder Ling’s equation Doran, Trans on Comp 9/88 Propagates information on two bits

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Prof. V.G. OklobdzijaVLSI Arithmetic57 Ling Adder Conventional: Ling:

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Prof. V.G. OklobdzijaVLSI Arithmetic58 S. Naffziger, ISSCC’96

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Prof. V.G. OklobdzijaVLSI Arithmetic59 S. Naffziger, ISSCC’96

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Prof. V.G. OklobdzijaVLSI Arithmetic60 S. Naffziger, ISSCC’96

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Prof. V.G. OklobdzijaVLSI Arithmetic61 S. Naffziger, ISSCC’96

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Prof. V.G. OklobdzijaVLSI Arithmetic62 S. Naffziger, ISSCC’96

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Prof. V.G. OklobdzijaVLSI Arithmetic63 S. Naffziger, ISSCC’96

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Prof. V.G. OklobdzijaVLSI Arithmetic64 S. Naffziger, ISSCC’96

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Prof. V.G. OklobdzijaVLSI Arithmetic65 S. Naffziger, ISSCC’96

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Prof. V.G. OklobdzijaVLSI Arithmetic66 S. Naffziger, ISSCC’96

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Prof. V.G. OklobdzijaVLSI Arithmetic67 S. Naffziger, ISSCC’96

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Prof. V.G. OklobdzijaVLSI Arithmetic68 S. Naffziger, ISSCC’96

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Prof. V.G. OklobdzijaVLSI Arithmetic69 Results: S. Naffziger, “A Subnanosecond 64-b Adder”, ISSCC ‘ 96 0.5u Technology Speed: 0.930 nS Nominal process, 80C, V=3.3V

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Prof. V.G. OklobdzijaVLSI Arithmetic70 ConditionalSum Adder J. Sklansky, “Conditional-Sum Addition Logic”, IRE Transactions on Electronic Computers, EC-9, p.226-231, 1960.

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Prof. V.G. OklobdzijaVLSI Arithmetic71 Conditional Sum Adder

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Prof. V.G. OklobdzijaVLSI Arithmetic72 ConditionalSum Adder

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Prof. V.G. OklobdzijaVLSI Arithmetic73 Carry-Select Adder O. J. Bedrij, “Carry-Select Adder”, IRE Transactions on Electronic Computers, June 1962, p.340-34

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Prof. V.G. OklobdzijaVLSI Arithmetic74 Carry-Select Adder Addition under assumption of C in =0 and C in =1.

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Prof. V.G. OklobdzijaVLSI Arithmetic75 Carry Select Adder: combining two 32-b VBAs in select mode Delay = VBA32 + MUX

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Prof. V.G. OklobdzijaVLSI Arithmetic76 Addition Under Non-equal Signal Arrival Profile Assumption P. Stelling, V. G. Oklobdzija, "Design Strategies for Optimal Hybrid Final Adders in a Parallel Multiplier", special issue on VLSI Arithmetic, Journal of VLSI Signal Processing, Kluwer Academic Publishers, Vol.14, No.3, December 1996

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Prof. V.G. OklobdzijaVLSI Arithmetic77 Signal Arrival Profile form the Parallel Multiplier Partial-Product Recuction Tree

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Prof. V.G. OklobdzijaVLSI Arithmetic78 Oklobdzija, Villeger, IEEE Transactions on VLSI Systems, June, 1995

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Prof. V.G. OklobdzijaVLSI Arithmetic79 Oklobdzija and Villeger, IEEE Transactions on VLSI Systems, June, 1995

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Prof. V.G. OklobdzijaVLSI Arithmetic88 Performing Multiply-Add Operation in the Multiply Time P. Stelling, V. G. Oklobdzija, " Achieving Multiply-Accumulate Operation in the Multiply Time", Thirteenth International Symposium on Computer Arithmetic, Pacific Grove, California, July 5 - 9, 1997.

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Prof. V.G. OklobdzijaVLSI Arithmetic89

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Prof. V.G. OklobdzijaVLSI Arithmetic90 Final Adder: Implementation

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Prof. V.G. OklobdzijaVLSI Arithmetic91 Final Adder: Implementation

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Prof. V.G. OklobdzijaVLSI Arithmetic92 Final Adder: Implementation

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Prof. V.G. OklobdzijaVLSI Arithmetic93 Final Adder: Implementation

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Prof. V.G. OklobdzijaVLSI Arithmetic94 Recurrence Solver Based Adders Koggie and Stone, IEEE Trans on Computers, August 1973 Bilgory and Gajski, 18 th DAC, 1981 Brent and Kung, IEEE Trans on Computers, March 1982

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Prof. V.G. OklobdzijaVLSI Arithmetic95 Recurrence Solver Based Adders 1973, Koggie and Stone published a general recurrence scheme for parallel computation 1979, Brent and Kung published Tech. Report on regular layout for parallel adders 1980, Guibas and Vuillemin, developed a layout scheme based on recurrence equation for addition 1980, Ladner and Fisher published “parallel prefix computation”, Jo of ACM 1981, Bilgory and Gajski published a paper on recurrence structures for automatic cell generation

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Prof. V.G. OklobdzijaVLSI Arithmetic96 Recurrence Solver Based Adders They are based on recurrence equation for P,G (what is new there since Weinberger ?!!): Or:and

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Prof. V.G. OklobdzijaVLSI Arithmetic97 Recurrence Solver Based Adders

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Prof. V.G. OklobdzijaVLSI Arithmetic98 Carry-Lookahead Adder (Weinberger and Smith) Just to remind you ! please notice the similarity with Parallel-Prefix Adders !

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Prof. V.G. OklobdzijaVLSI Arithmetic99 Multiplexer Based Adder Farooqui and Oklobdzija 1999 Int’l Sym. on VLSI Technology, Taipei, Taiwan, June 8-10, 1999

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Prof. V.G. OklobdzijaVLSI Arithmetic100 Multiplexer Based Adder Based on the realization that MUX circuit is faster than a logic gate due to its transmission gate implementation Based on Carry-Lookahead method (W-S), or recurrence solver.

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Prof. V.G. OklobdzijaVLSI Arithmetic101 Multiplexer Based Adder A. A. Farooqui, V. G. Oklobdzija, F. Chechrazi, 1999 Int’l Sym. on VLSI Technology, Taipei, Taiwan, June 8-10, 1999.

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Prof. V.G. OklobdzijaVLSI Arithmetic102 Multiplexer Based Adder A. A. Farooqui, V. G. Oklobdzija, F. Chechrazi, 1999 Int’l Sym. on VLSI Technology, Taipei, Taiwan, June 8-10, 1999.

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Prof. V.G. OklobdzijaVLSI Arithmetic103 Multiplexer Based Adder A. A. Farooqui, V. G. Oklobdzija, F. Chechrazi, 1999 Int’l Sym. on VLSI Technology, Taipei, Taiwan, June 8-10, 1999.

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Prof. V.G. OklobdzijaVLSI Arithmetic104 Multiplexer Based Adder A. A. Farooqui, V. G. Oklobdzija, F. Chechrazi, 1999 Int’l Sym. on VLSI Technology, Taipei, Taiwan, June 8-10, 1999. Results in a very fast structure 7-MUX delays for a 64-b adder Delay using standard cell 0.25u, 2.5V, 25 o C : Adder Size (bits) Delay (pS) 8625 16665 32710 64903

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Prof. V.G. OklobdzijaVLSI Arithmetic105 DEC "Alpha" 21064 Adder Combination: –8-bit tapered pre-discharged Manchester Carry Chains, with C in = 0 and C in = 1 –32-bit LSB Carry Lookahead Adder –32-bit MSB Conditional-Sum Adder –Carry-Select on most significant 32-bits –Latches in the middle: pipelined addition

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Prof. V.G. OklobdzijaVLSI Arithmetic106 DEC "Alpha" 21064 Adder

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Prof. V.G. OklobdzijaVLSI Arithmetic107 DEC "Alpha" 21064 Adder: Results The first 200MHz processor Built using 0.75u technology V=3.3V, 30W Pipelined (two-latches) allowing 5nS throughput and 10nS latency

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Prof. V.G. OklobdzijaVLSI Arithmetic108 Conclusion VLSI Implementation of Addition

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Prof. V.G. OklobdzijaVLSI Arithmetic109 Conclusion: VLSI Implementation of Addition Currently, implementation parameters are not reflected in algorithms used for development Layout and wire delays effects are largely neglected and this is becoming intolerable in the next generation of technology Transistor sizing has a large effect which can outweight the algorithm There is a great disconnect between algorithm and implementation New rules and measures of goodness are needed

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Prof. V.G. OklobdzijaVLSI Arithmetic110 Multiplication Parallel Multiplier Implementation

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Prof. V.G. OklobdzijaVLSI Arithmetic111 Multiplication Algorithm: for j=0,....,n-1 initially p(n)=XY after n steps

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Prof. V.G. OklobdzijaVLSI Arithmetic112 Parallel Multipliers

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Prof. V.G. OklobdzijaVLSI Arithmetic113 4:2 Compressor

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Prof. V.G. OklobdzijaVLSI Arithmetic114 Re-designed 4:2 Compressor with 3 XOR Delay C in I1 I2 I3 I4 0 1 S C C out

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Prof. V.G. OklobdzijaVLSI Arithmetic115 Three-Dimensional optimization Method: TDM (Oklobdzija, Villeger, Liu, 1996)

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Prof. V.G. OklobdzijaVLSI Arithmetic116 Generation of the Partial Product Reduction Tree in TDM multiplier

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Prof. V.G. OklobdzijaVLSI Arithmetic117 Speed of Partial Product Reduction for Various Schemes

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Prof. V.G. OklobdzijaVLSI Arithmetic118 Booth Recoding Algorithm x i+2 x i+1 x i Add to partial product 000+0Y 001+1Y 010+1Y 011+2Y 100-2Y 101-1Y 110-1Y 111-0Y

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Prof. V.G. OklobdzijaVLSI Arithmetic119 Organization of Hitachi's DPL multiplier

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Prof. V.G. OklobdzijaVLSI Arithmetic120 Hitachi's 4:2 compressor structure

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Prof. V.G. OklobdzijaVLSI Arithmetic121 DPL multiplexer circuit

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Prof. V.G. OklobdzijaVLSI Arithmetic122 Conclusion References: 1.E. Swartzlander, "Computer Arithmetic". Vol. 1&2, IEEE Computer Society Press, 1990. 2.K. Hwang, "Computer Arithmetic : Principles, Architecture and Design", John Wiley and Sons, 1979. 3.M. Ercegovac, “Digital Systems and Hardware/Firmware Algorithms”, Chapter 12: Arithmetic Algorithms and Processors, John Wiley & Sons, 1985. 4.A. Chandrakasan, W. Bowhill, F Fox, Editors, "Design of High Performance Microprocessors Circuits", IEEE Press, July 2000. 5.V. G. Oklobdzija, “High-Performance System Design: Circuits and Logic”, IEEE Press, July 1999. Also: http://www.ece.ucdavis.edu/acsel/Publications.html

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