1. 2’s Complement 4-Bit Saturator
Lecture L4.6

2. Equality Detector XNOR X Y Z 0 0 1 0 1 0 X 1 0 0 Z 1 1 1 Y X Z Y
Z = !(X $ Y)

3. Z = 1 if A=B=C

4. Multiplexers s1 s0 C0 C1 4 x 1 MUX Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2

5. Multiplexers 4 x 1 MUX s1 s0 C0 C1 Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2
A multiplexer is a
digital switch
0 0

6. Multiplexers 4 x 1 MUX s1 s0 C0 C1 Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2
0 1

7. Multiplexers 4 x 1 MUX s1 s0 C0 C1 Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2
1 0

8. Multiplexers 4 x 1 MUX s1 s0 C0 C1 Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2
1 1

9. A 2 x 1 MUX
Z = A & !s0 # B & s0

10. Problem How would you make a Quad 2-to-1 MUX?S
0 A
1 B
Quad
2-to-1
MUX
[A3..A0]
[Y3..Y0]
[B3..B0] S

11. X =
Y = 0111
X =
Y = 1000
NASA Tech Briefs
November 2001 A Y0 Y1 Y2 Y3 X0 X1 X2 B X3 X4 X5 c0
X =
Y = 1111
X =
Y = 0101 c1

12. ABEL // Title: 2s-complement 4-bit Saturator // Author: R. E. Haskell
// Ref: NASA Tech Briefs, Nov. 2001
// Description: 4-bit output Y =
// if 6-bit input X is <= -8
// if 6-bit input X is >= +7
// X otherwise
MODULE sat64
INTERFACE ([X5..X0] -> [Y3..Y0]);
TITLE '2s complement 4-bit saturator'
// Author: R. E. Haskell

13. DECLARATIONS " Input Pins " X5..X0 PIN ISTYPE 'com';
X = [X5..X0]; " 6-bit input
" Output Pins "
Y3..Y0 PIN ISTYPE 'com';
Y = [Y3..Y0]; " 4-bit output
"Definitions
A = [X5,!X5,!X5,!X5];
B = [X3,X2,X1,X0];
c0 = !(X3 $ X4);
c1 = !(X4 $ X5);
s = c0 & c1;
EQUATIONS
Y = !s & A # s & B;
END A Y0 Y1 Y2 Y3 X0 X1 X2 B X3 X4 X5 c0 c1

14. Top-level Design

15. // Title: Absolute value function
// Author: R. E. Haskell
// Input: Y = 4-bit signed number (-8 to +7)
// Output: Z = magnitude of input number (0 to 8)
MODULE absval
interface([Y3..Y0] -> [Z3..Z0]);
DECLARATIONS
" INPUT PINS "
Y3..Y0 PIN;
Y = [Y3..Y0]; " 4-bit input
" OUTPUT PINS "
Z3..Z0 PIN ISTYPE 'com';
Z = [Z3..Z0]; " 4-bit output

16. DECLARATIONS
" INPUT PINS "
Y3..Y0 PIN;
Y = [Y3..Y0]; " 4-bit input
" OUTPUT PINS "
Z3..Z0 PIN ISTYPE 'com';
Z = [Z3..Z0]; " 4-bit output
EQUATIONS
when (Y == 0) then Z = ^b0000;
when (Y == 1) then Z = ^b0001;
when (Y == 2) then Z = ^b0010;
when (Y == 3) then Z = ^b0011;
when (Y == 4) then Z = ^b0100;
when (Y == 5) then Z = ^b0101;
when (Y == 6) then Z = ^b0110;
when (Y == 7) then Z = ^b0111;
when (Y == 8) then Z = ^b1000;
when (Y == 9) then Z = ^b0111;
when (Y == ^h0A) then Z = ^b0110;
when (Y == ^h0B) then Z = ^b0101;
when (Y == ^h0C) then Z = ^b0100;
when (Y == ^h0D) then Z = ^b0011;
when (Y == ^h0E) then Z = ^b0010;
when (Y == ^h0F) then Z = ^b0001;
END absval

17. Top-level Design

18. // Title : 2's Complement 4-Bit Saturator
// Author : R. E. Haskell
// Description : 7-segment displays show the signed output
// of the 2's complement 4-bit saturator
MODULE sat4bit
DECLARATIONS
sat64 INTERFACE ([X5..X0] -> [Y3..Y0]);
sat FUNCTIONAL_BLOCK sat64;
absval INTERFACE ([Y3..Y0] -> [Z3..Z0]);
abs FUNCTIONAL_BLOCK absval;
hex7seg INTERFACE ([D3..D0] -> [a,b,c,d,e,f,g]);
d7R FUNCTIONAL_BLOCK hex7seg;

19. " INPUT PINS "
SW5..SW0 PIN 6,5,4,3,2,1; " S6, Switches 3,4; S7, Switches 1-4
SW = [SW5..SW0];
" OUTPUT PINS "
LEDR3..LEDR0 PIN 40,41,43,44 ISTYPE 'com'; " LEDs 13-16
LEDR = [LEDR3..LEDR0];
[a,b,c,d,e,f,g] PIN 15,18,23,21,19,14,17 ISTYPE 'com';
Rsegments = [a,b,c,d,e,f,g]; " Rightmost 7-segment digit
minus PIN 66 ISTYPE 'com'; " segment g of left 7seg display
EQUATIONS
sat.[X5..X0] = SW;
LEDR = sat.[Y3..Y0];
abs.[Y3..Y0] = sat.[Y3..Y0];
d7R.[D3..D0] = abs.[Z3..Z0];
Rsegments = d7R.[a,b,c,d,e,f,g];
minus = sat.Y3;
END

20. Verilog // Title: 2s-complement 4-bit Saturator
// Author: R. E. Haskell
// Ref: NASA Tech Briefs, Nov. 2001
// Description: 4-bit output Y =
// -8 if 6-bit input X is <= -8
// +7 if 6-bit input X is >= +7
// X otherwise
module sat64(X,Y);
input [5:0] X;
output [3:0] Y;

21. assign A[2:0] = {~X[5],~X[5],~X[5]}; assign B = {X[3],X[2],X[1],X[0]};
module sat64(X,Y);
input [5:0] X;
output [3:0] Y;
wire [3:0] Y;
wire c0, c1, s;
wire [3:0] A;
wire [3:0] B;
assign A[3] = X[5];
assign A[2:0] = {~X[5],~X[5],~X[5]};
assign B = {X[3],X[2],X[1],X[0]};
assign c1 = X[3] ~^ X[4];
assign c0 = X[4] ~^ X[5];
assign s = c0 & c1;
assign Y = {4{~s}} & A | {4{s}} & B;
endmodule A Y0 Y1 Y2 Y3 X0 X1 X2 B X3 X4 X5 c0 c1

22. Top-level Design

23. // Title: Absolute value function
// Author: R. E. Haskell
// Input: Y = 4-bit signed number (-8 to +7)
// Output: Z = magnitude of input number (0 to 8)
module absval(Y,Z);
input [3:0] Y;
output [3:0] Z;
reg [3:0] Z;

24. module absval(Y,Z);
input [3:0] Y;
output [3:0] Z;
reg [3:0] Z;
case(Y)
0: Z = 4'b0000;
1: Z = 4'b0001;
2: Z = 4'b0010;
3: Z = 4'b0011;
4: Z = 4'b0100;
5: Z = 4'b0101;
6: Z = 4'b0110;
7: Z = 4'b0111;
8: Z = 4'b1000;
9: Z = 4'b0111;
'hA: Z = 4'b0110;
'hb: Z = 4'b0101;
'hC: Z = 4'b0100;
'hd: Z = 4'b0011;
'hE: Z = 4'b0010;
'hF: Z = 4'b0001;
default: Z = 4'b0000; // 0
endcase
endmodule

25. Top-level Design

26. // Title : 2's Complement 4-Bit Saturator
// Author : R. E. Haskell
// Description : 7-segment displays show the signed output // of the 2's complement 4-bit saturator
module sat4bit(SW,LEDR,LEDG,AtoG,gg);
input [5:0] SW;
output [3:0] LEDR;
output [5:0]LEDG;
output [6:0] AtoG;
output gg;

27. module sat4bit(SW,LEDR,LEDG,AtoG,gg);
input [5:0] SW;
output [3:0] LEDR;
output [5:0]LEDG;
output [6:0] AtoG;
output gg;
wire [6:0] AtoG;
wire [3:0] LEDR;
wire [5:0] LEDG;
wire gg;
wire [3:0] Y;
wire [3:0] Z;
assign LEDR = Y;
assign LEDG = SW;
assign gg = Y[3];
sat64 sat(.X(SW),.Y(Y));
hex7seg d7R(.D(Z),.AtoG(AtoG));
absval abs(.Y(Y),.Z(Z));
endmodule