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CSULB -- CECS 201– Verilog Basics © 2013 -- R.W. Allison 1.

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Presentation on theme: "CSULB -- CECS 201– Verilog Basics © 2013 -- R.W. Allison 1."— Presentation transcript:

1 CSULB -- CECS 201– Verilog Basics © R.W. Allison 1

2 2 Behavioral Use always block Outputs declared as reg Combinational Logic Sequential Logic (*) (posedge clk, posedge reset) case ( {all inputs} ) if ( reset == 1b1 ) //check for reset first // assign output(s) for reset condition // each row assigns output(s) // based on input combinations else //got a clock // assign output(s) based on decisions Structural DO NOT use always Outputs declared as wire Instantiate other modules and interconnect them with wires and busses… Schematics using text CSULB -- CECS 201– Verilog Basics © R.W. Allison … or, alternatively, use the assign statement along with the verilog operators for and (&), or (|), not (~) and xor (^). For example, assign F1 = (~W & X & ~Y) | (~X & ~Z);

3 3 module addsub4 ( M, A, B, Cin, Y, CB ); Module name (must begin with a letter or underscore) Port list (input and output names) input [3:0] A, B; input M, Cin; output wire [3:0] Y; output wire CB; input/output declarations size specifier (default size is 1-bit scalar) // structural logic of 4-bit add/sub // using 4 instances of 1-bit addsub addsub a0 ( M, A[0], B[0], Cin, Y[0], cb0), a1 ( M, A[1], B[1], cb0, Y[1], cb1), a2 ( M, A[2], B[2], cb1, Y[2], cb2), a3 ( M, A[3], B[3], cb2, Y[3], CB); single line comments endmodule CSULB -- CECS 201– Verilog Basics © R.W. Allison type specifier (for outputs only, default type is wire)

4 4 module addsub ( M, A, B, Cin, Y, CB ); Module name (must begin with a letter or underscore) Port list (input and output names) input [3:0] A, B; input M, Cin; output reg [3:0] Y; output reg CB; input/output declarations size specifier (default size is 1-bit scalar) ( M, A, B, Cin ) begin event operator sensitivity list // behavioral logic of add/sub if ( M == 1b0 ) {CB,Y} = A + B + Cin; else {CB,Y} = A - B - Cin; end // end of always single line comment endmodule concatenation operator Note: Verilog is an event driven language, not a sequential language. As such, the most powerful operator in the verilog language is the event operator In practical use, the second most powerful operator is the concatenation operator ( {, } ). CSULB -- CECS 201– Verilog Basics © R.W. Allison type specifier (for outputs only)

5 5 CSULB -- CECS 201– Verilog Basics © R.W. Allison En I1 I0 Y3 Y2 Y1 Y One could create four 3-variable K-maps to find the S.O.P expressions for the four outputs, but, by observation, each output only has one minterm in the truth table where it is 1. Thus,Y3 = En & I1 & I0 Y2 = En & I1 & I0 Y1 = En & I1 & I0 Y2 = En & I1 & I0 I1 I0 En Y3 Y2 Y1 Y0 decode_2to4

6 6 CSULB -- CECS 201– Verilog Basics © R.W. Allison module decoder_2to4 (En, I1, I0, Y3, Y2, Y1, Y0); input En, I1, I0; output wire Y3, Y2, Y1, Y0; wire i1_n, i0_n; // interconnection wires for not gate outputs // Structural model of decoder using 4 3-input and gates not n1 (i1_n, I1), n0 (i0_n, I0); and ag3 (Y3, En, I1, I0), ag2 (Y2, En, I1, i0_n), ag1 (Y1, En, i1_n, I0), ag0 (Y0, En, i1_n, i0_n); endmodule Thus,Y3 = En & I1 & I0 Y2 = En & I1 & I0 Y1 = En & I1 & I0 Y2 = En & I1 & I0 Structural using gates

7 7 CSULB -- CECS 201– Verilog Basics © R.W. Allison module decoder_2to4 (En, I1, I0, Y3, Y2, Y1, Y0); input En, I1, I0; output wire Y3, Y2, Y1, Y0; // Structural model of decoder using 4 3-input assign statement assign Y3 = (En & I1 & I0), Y2 = (En & I1 & ~I0), Y1 = (En & ~I1 & I0), Y0 = (En & ~I1 & ~I0); endmodule Thus,Y3 = En & I1 & I0 Y2 = En & I1 & I0 Y1 = En & I1 & I0 Y2 = En & I1 & I0 Structural using assign

8 8 CSULB -- CECS 201– Verilog Basics © R.W. Allison En I1 I0 Y3 Y2 Y1 Y Having the truth table for ANY logic function, we can create a behavioral module using the verilog case statement. In essence, the case statement has exactly the same input/output relationships seen in a table; I1 I0 En Y3 Y2 Y1 Y0 decode_2to4 // behavioral logic of 2-to-4 decoder case ( {En, I1, I0} ) 3b000: {Y3,Y2,Y1,Y0} = 4b0000; 3b001: {Y3,Y2,Y1,Y0} = 4b0000; 3b010: {Y3,Y2,Y1,Y0} = 4b0000; 3b011: {Y3,Y2,Y1,Y0} = 4b0000; 3b100: {Y3,Y2,Y1,Y0} = 4b0001; 3b101: {Y3,Y2,Y1,Y0} = 4b0010; 3b110: {Y3,Y2,Y1,Y0} = 4b0100; 3b111: {Y3,Y2,Y1,Y0} = 4b1000; endcase Inputs Outputs yet the table data must be placed in the case template.

9 module decoder_2to4 ( En, I1, I0, Y3, Y2, Y1, Y0); input En, I1, I0; output reg Y3, Y2, Y1, Y0; endmodule 9 CSULB -- CECS 201– Verilog Basics © R.W. Allison The case statement must be placed within the verilog always block, the only procedural block used in behavioral modeling. case ( {En, I1, I0} ) 3b000: {Y3,Y2,Y1,Y0} = 4b0000; 3b001: {Y3,Y2,Y1,Y0} = 4b0000; 3b010: {Y3,Y2,Y1,Y0} = 4b0000; 3b011: {Y3,Y2,Y1,Y0} = 4b0000; 3b100: {Y3,Y2,Y1,Y0} = 4b0001; 3b101: {Y3,Y2,Y1,Y0} = 4b0010; 3b110: {Y3,Y2,Y1,Y0} = 4b0100; 3b111: {Y3,Y2,Y1,Y0} = 4b1000; endcase The complete module is created by packaging the procedural block within the applicable verilog module declarations... // behavioral logic of 2-to-4 decoder (En, I1, I0) begin end // end of always block // Although verilog allows for free // formatting, you are encouraged to // develop good coding style. // Programming styles commonly deal // with the visual appearance of source // code, with the goal of requiring less // human cognitive effort to extract // information about the program. 1 1 ref.


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