Download presentation

Presentation is loading. Please wait.

Published byKimberly Hansen Modified over 2 years ago

1
CSE 370 Sample Final Exam Questions

2
1) Logic Minimization CD AB F = Σm(0,6,7,8,9,11,15) + d(1,13)

3
1) Logic Minimization 11 dd CD AB F = Σm(0,6,7,8,9,11,15) + d(1,13)

4
1) Prime Implicants 11 dd CD AB Note: Prime Implicant = largest box covering a 1

5
1) Essential PIs 11 dd CD AB Note: Essential PI = PIs that cover a 1 not covered by any other PIs

6
1) Logic Minimization 11 dd CD AB Prime Implicants: BC, AD, ABC, BCD Essential Prime Implicants: BC, AD, ABC Minimal Cover: F = BC + AD + ABC

7
2a) Gates to Functions back into Gates FG H

8
FG H Z = ~(H + G) Z = ~H & ~G Z = ~(~(C+D)) & ~(~(F+F)) Z = (C+D) & F Z = (C+D) & ~(A+B) Z = (C+D) & ~A & ~B Z = ABC + ABD

9
2b) Gates to Functions back into Gates Z = ABC + ABD Using deMorgans Law… Z = ~(~(ABC) & ~(ABD)) C A B D

10
2c) Gates to Functions back into Gates NOR Circuit 3 gate 7ns 21ns total NAND Circuit 2 gate 9ns 18ns total

11
3a) Multiplexer Logic Z = BC + ABD + AB ABCDZ

12
3a) Multiplexer Logic Z = BC + ABD + AB ABCDZ

13
3a) Multiplexer Logic Z = BC + ABD + AB ABCDZ

14
3a) Multiplexer Logic Z = BC + ABD + AB ABCDZ

15
3a) Multiplexer Logic Z = BC + ABD + AB ABCDZ

16
3b) Multiplexer Logic S3S2S1S0 16:1 MUX Z = BC + ABD + AB ABCD

17
3c) Multiplexer Logic S2S1S0 8:1 MUXZ = BC + ABD + AB 1111 ABC 1DD11DD1 1DD111DD11 01DD110001DD1100 Note: Requires no extra logic

18
4) Decoder Logic W = (A xor C) + B ABCW

19
4) Decoder Implementation S2S1S0 3:8 DEC ABC W = (A xor C) + B EN1

20
5) Programmable Logic X Y Note: 2 Common Prime Implicants can be used by X and Y Z = ABCD + ABCD X = Z + ABCD + ABCD Y = Z + ABC + ABC

21
5) Programmable Logic Z = ABCD + ABCD X = Z + ABCD + ABCD Y = Z + ABC + ABC Z = ABCD + ABCD X = Z + ABCD + ABCD Y = Z + ABC + ABC

22
6) Verilog to Circuit

23
7) Circuit to Verilog

24
module maxValue (DataOut, strobe, Data); // Port Definitions output reg [7:0] DataOut; input strobe; input [7:0] Data; // Behavioral Statements for DataOut // other required internal signals endmodule

25
7) Circuit to Verilog // Behavioral Statements for DataOut (posedge clk) begin if (regEnable) DataOut <= Data; else DataOut <= DataOut; end

26
7) Circuit to Verilog regEnable strobeNegedge prevStrobe[2] prevStrobe[1] prevStrobe[0]

27
7) Circuit to Verilog // other required internal signals wire regEnable, strobeNegedge; reg prevStrobe[2:0]; assign regEnable = (Data > DataOut) && strobeNegedge assign strobeNegedge = prevStrobe[2] & ~prevStrobe[1]; (posedge clk) prevStrobe = {prevStrobe[1:0],strobe};

28
8) Carry Look-ahead Adder Recall: Sum = A xor B xor C Cout = AB + BC + AC Rewrite Cout: Cout = AB + C (A + B)

29
8) Carry Look-ahead Adder ABP XOR P OR 2 functions are only different if A and B are 1

30
8) Carry Look-ahead Adder Need carry out if A and B are 1 carry is generated in this case dont need propagate to cover this case these are then functionally equivalent Recall: Sum = A xor B xor C P = A + B: have to calculate A xor B P = A xor B: reuse this to compute Sum P = A xor B uses less logic

31
9) Verilog State Machine ABS[1]NS[0]NS[1]S[0]out

32
9) Verilog State Machine S[1:0] AB out NS[1] NS[0] S[1:0] AB S[1:0] AB NS[1]=S[0]B + S[1]S[0] NS[0] = S[1]S[0]B + S[1]S[0]A + S[1]S[0]B + S[1]S[0]A out = S[1]S[0]AB + S[1]S[0]AB + S[1]S[0]AB + S[1]S[0]AB

33
9) Verilog State Machine

34
10) Design: Parallel to Serial Shift Register Load parallel data Shift out serial data Counter How many bits have shifted out Controller Shift Enable Done Shifting

35
10a) Design: Parallel to Serial Shifter dataIn load dataOut Counter reset clk count char[7:0] start reset clk Controller clk sdata done Datapath start reset count load reset_cnt done

36
10b) Design: Parallel to Serial Can we collapse these to 1 state?

37
10b) Design: Parallel to Serial

38
10c) Design: Parallel to Serial Shifter dataIn[8:0] load dataOut[8:0] Counter reset clk count clk sdata= dataOut[0] done = state[1] {char,1b0} start clk dataOut[8:0] Register nextState[1] clk state Note: Shifter shifts in 1 in MSB clk count[3:0] clk state[1:0] start + state[1] + state[1:0]==0 + ((state==1)&&(count==4hA) ~start && (state==1) && (count==4hA) nextState[0] start + ((state==1)&&(count<4hA)) char[7:0] start reset clk

39
11) x370 CALL Instruction CALL Requirements Load address into PC from instruction Store PC+1 into RD

40
11) Implementation Load address into PC inst[5:0] muxed to input of PC Load PC asserted Store PC+1 into RD PC muxed to A input of ALU ALU inst set to INC ALU output muxed to reg write data Reg write address set to R D

41
Final Questions?

Similar presentations

© 2016 SlidePlayer.com Inc.

All rights reserved.

Ads by Google