# Digital System Design-II (CSEB312)

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Digital System Design-II (CSEB312)
Verilog Tutorial Part - 1

Topics Introduction Combinational Logic Structural Modeling Behavioral Modeling

Most commercial designs built using HDLs Two leading HDLs:
Introduction Hardware description language (HDL): allows designer to specify logic function only. Then a computer-aided design (CAD) tool produces the optimized gates. Most commercial designs built using HDLs Two leading HDLs: Verilog developed in 1984 by Gateway Design Automation became an IEEE standard (1364) in 1995 VHDL Developed in 1981 by the Department of Defense Became an IEEE standard (1076) in 1987

HDL to Gates Simulation Synthesis IMPORTANT:
Input values are applied to the circuit Outputs checked for correctness Millions of dollars saved by debugging in simulation instead of hardware Synthesis Transforms HDL code into a netlist describing the hardware (i.e., a list of gates and the wires connecting them) IMPORTANT: When describing circuits using an HDL, it’s critical to think of the hardware the code should produce.

Modules have inputs and outputs
Verilog Modules Module is a block of circuit that performs a special function. Simple functions are and, or, etc. Somewhat larger functions/operations are multiplexers, adders, multipliers, etc. Modules have inputs and outputs

Behavioral: describe what a module does
Verilog Modules Two types of Modules: Behavioral: describe what a module does Structural: describe how a module is built from simpler modules

A Verilog Module

Behavioral Verilog Example
module example(input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule

Behavioral Verilog Simulation
module example(a, b, c, y); input a, b, c; output y; assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule

In class practice

In class practice Write code for this circuit:

Verilog Stimuli module TB(); reg outA, outB, clk; // DUT input
//wire Gout; // DUT output // once only initial begin #0 outA = 1'b0; outB = 1'b0; #20 outA = 1'b0; outB = 1'b1; #20 outA = 1'b1; outB = 1'b0; #20 outA = 1'b1; outB = 1'b1; #20 outA = 1'b0; outB = 1'b0; end // clock generator clk = 1'b0; forever begin #15 clk = 1'b0; #15 clk = 1'b1; endmodule

Practice question

Behavioral Verilog Implementation
module comb_circ(a, b, c, y); input a, b, c; output y; assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule Circuit:

Port Declaration All ports must be declared as:
input, output, or inout (A top-level module may not have a list of ports) All input/output ports are implicitly declared as wires. If an output port needs to hold a value, declare as reg. input inout output net (net) (reg OR net) reg OR net Port connection rules

Behavioral & Structural Code Examples
// BEHAVORAL code: A demultiplexer module demux ( D, select, y0, y1); input D, select; output y0,y1; assign y0 = (~select) & D; assign y1 = select & D; endmodule D y0 Select y1 a // STRUCTURAL code: A demultiplexer module demux ( D, select, y0, y1); input D, select; output y0,y1; wire a; // What is a wire? Internal nodes! More later. not g0 (a, select); and g1 (y0, D, a); and g2 (y1, D, select); endmodule

module exerc1 ( input x, y, z, u, output q ); wire w1, w2; and g0(w1, x, y, z); not g1(w2, u); or g2(a, w1, w2); endmodule

Verilog Syntax – General Notes
Verilog is case sensitive. So, reset and Reset are not the same signal. Verilog does not allow you to start signal or module names with numbers. So, for example, 2mux is an invalid name. Verilog ignores whitespaces. Comments come in single-line and multi-line varieties: // single line comment /* multiline comment */ Avoid syntax pitfalls: Use pairs of module and endmodule. Use pairs of begin and end. Type module(), not Module(). Add “;” symbol for the end of every statement. Ensure a match between the number of port or the number of pins of some buses.

Bitwise Operators module gates(a, b, clk, sel, u, v, w, x, y);
input [3:0] a, b; // each bus is 4 wires input clk; // one-bit input input [1:0] sel; // sel is 2-bit input output [3:0] u, v, w, x, y; /* Five different two-input logic gates acting on 4 bit buses */ assign u = a & b; // AND assign v = a | b; // OR assign w = a ^ b; // XOR assign x = ~(a & b); // NAND assign y = ~(a | b); // NOR endmodule

Reduction Operators module and8(a,y); input [7:0]a; output y; assign y = &a; // &a is much easier to write than the following: // assign y = a[7] & a[6] & a[5] & a[4] & // a[3] & a[2] & a[1] & a[0]; endmodule

Conditional Assignment
? : is also called a ternary operator because it operates on 3 inputs: s, d1, and d0. module mux2(d0, d1, s, y); input [3:0] d0, d1; input s; output [3:0] y); assign y = s ? d1 : d0; // y = s ? True : False // if s is true, y = d1 // else y = d0 endmodule

Internal Variables (wires)
module fulladder(a, b, cin, s, cout); input a, b, cin; output s, cout; wire p, g; // internal nodes assign p = a ^ b; assign g = a & b; assign s = p ^ cin; assign cout = g | (p & cin); endmodule

Operator Precedence Highest Lowest Defines the order of operations ~
NOT *, /, % mult, div, mod +, - add, sub <<, >> Logical shift <<<, >>> arithmetic shift <, <=, >, >= comparison ==, != equal, not equal &, ~& AND, NAND ^, ~^ XOR, XNOR |, ~| OR, XOR ?: ternary operator Lowest y = enb ? Tru : Fls

Numbers Format: N'Bvalue N = number of bits, B = base
N'B is optional but recommended (default is decimal) Number # Bits Base Decimal Equivalent Stored 3’b101 3 binary 5 101 ‘b11 unsized 00…0011 8’b11 8 8’b1010_1011 171 3’d6 decimal 6 110 6’o42 octal 34 100010 8’hAB hexadecimal 42 Unsized 00… Caution: Ensure proper number of bits while assigning values. For example, the result is not right, if 2’d12 is assigned to 3-bit bus; need 4 bits in this case.

Modeling Hierarchy module and3(a, b, c, y); input a, b, c; output y;
assign y = a & b & c; endmodule module inv(a, y); input a; assign y = ~a; module nand3(a, b, c, y); wire out; // internal signal and3 andgate(a, b, c, out); // instance of and3 inv inverter(out, y); // instance of inverter

Modeling Hierarchy – Example
Using the same module many times Example: Constructing 4-bit adder using four one-bit adders Adder a [3:0] b [3:0] S [4:0] A a1 a0 a2 a3 b1 b0 b2 b3 s1 s0 s2 s3 s4 c3 c2 c1 c0 c0

Modeling Hierarchy – Example (contd.)
// One bit adder (behavioral) module Adder(a, b, carryin, result, carryout); input a, b, carryin; output result, carryout; wire a, b, result, carryout; assign result = a ^ b ^ carryin; assign carryout = (a & b) | (a & carryin) | (b & carryin); endmodule y x cout A cin sum

Modeling Hierarchy – Example (contd.)
// 4-bit adder using 4 one-bit adders module Adder4(x, y, cin, sum); input [3:0] x, y; input cin; output [4:0] sum; wire c[3:1]; // Instantiate FOUR one-bit adders Adder A1(x[0], y[0], cin, sum[0], c[1]); Adder A2(x[1], y[1], c[1], sum[1], c[2]); Adder A3(x[2], y[2], c[2], sum[2], c[3]); Adder A4(x[3], y[3], c[3], sum[3], sum[4]); endmodule Adder(a, b, carryin, result, carryout); A a1 a0 a2 a3 b1 b0 b2 b3 s1 s0 s2 s3 s4 c3 c2 c1 cin

Bit Manipulations: Example 1
assign y = { a[2:1], { 3{b[0]} }, a[0], 6’b100_010 }; // if y is a 12-bit signal, the above statement produces: y = a[2] a[1] b[0] b[0] b[0] a[0] // underscores (_) are used for formatting only to make it easier to read. Verilog ignores them.

Bit Manipulations: Example 2
Verilog: module mux2_8(input [7:0] d0, d1, input s, output [7:0] y); mux2 lsbmux(d0[3:0], d1[3:0], s, y[3:0]); mux2 msbmux(d0[7:4], d1[7:4], s, y[7:4]); endmodule Circuit:

Z: Floating Output Verilog: Circuit: module tristate(input [3:0] a,
input en, output [3:0] y); assign y = en ? a : 4'bz; endmodule Circuit:

Delays module example(input a, b, c, output y); wire ab, bb, cb, n1, n2, n3; assign #1 {ab, bb, cb} = ~{a, b, c}; assign #2 n1 = ab & bb & cb; assign #2 n2 = a & bb & cb; assign #2 n3 = a & bb & c; assign #4 y = n1 | n2 | n3; endmodule

Delays HW1 due next week! Quiz-1 next week.
module example(input a, b, c, output y); wire ab, bb, cb, n1, n2, n3; assign #1 {ab, bb, cb} = ~{a, b, c}; assign #2 n1 = ab & bb & cb; assign #2 n2 = a & bb & cb; assign #2 n3 = a & bb & c; assign #4 y = n1 | n2 | n3; endmodule HW1 due next week! Quiz-1 next week.