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Boolean Algebra Application to electric switches (open - 0, closed - 1): a b c 220V~ L L = (a + b)c = ac + bc b c 220V~ L L = ac + bc c a Variables: only 2 values (0,1) Huntingtons (1804) axioms: 1 1 = = 0 a 0 = 0 a + 1 = 1 a a = 0 a + a = 1 a b = b a a + b = b + a a(b+c)=ab+ac a+bc=(a+b)(a+c) Verification by truth table: abc (a+b)c ac+bc Every logical function can be specified by truth table and implemented as sum of product form,e.g. L = abc + abc + abc.

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a+b Combinational Circuits a a NOT OR a b a+b Switch light L implemented by gates L = abc + abc + abc sum of products. Function presentation by Karnough map every product term has a field, and neighboring fields differ by only one variable. Example (three input variables): L = abc + abc + abc = abc + abc + abc + abc = ac(b + b) + bc(a + a) = ac + bc = (a + b)c Output is direct function of inputs b a c L a b ab a b c L a b c L

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2 Decoders and Multiplexers Decoder has n inputs and 2 n outputs: ABAB BA Mux determines which input will connect to output: S[1:0] A B C D OUT S

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Binary Adder Design a0a0 a3a3 a2a2 a1a1 b3b3 b2b2 b1b1 b0b0 c3c3 c2c2 c1c1 c0c0 c4c4 s3s3 s2s2 s1s1 s0s0 ab s coco cici Truth Table a b c i s c o Karnough maps a b cici a b cici s = ab c i +ab c i +ab c i +ab c i = (ab + ab)c i + (ab + ab)c i = (a + b) + c i = a + b + c i c o = ab + ac i + bc i a b c i s coco

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Programmable Logic Arrays PLA X ABCABC Y Any logical function can be implemented by two levels circuits: ANDs and ORs.

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c a b p CC a b p 0 0 stable x a p b time c b a p x x a: 1 0 a: 0 1 b: 1 0 b: 0 1 c b a x x p = a + bc b p c a p a b p Design of the RS flip-flop

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Registers One bit register = memory cell WE = Clock pulse in bit gate RS out bit WE b5b5 b4b4 b3b3 b2b2 b1b1 b7b7 b6b6 b0b0 Eight bit register

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The Concept of Memory address decoderaddress decoder N address lines (bus) address space = 2 N M data lines (bus) WE memory 0 memory 1 memory 2 memory 3 memory 4 memory 5 memory 6 memory 7 Memory as array of registers: address space and addressability

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Memory details word select word WE address write enable input bits output bits

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Q Q K J CL A opens master accepts B opens slave accepts B closes A A B B A closes master slave At no time the path between inputs JK and outputs QQ is closed. Design of the JK flip-flop

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CC clock A B Input Output Present state Next state * Output is a function of Input and Present state. * Next state is a function of Input and Present state. * Present state is delayed Next state. Synchronous Sequential Circuit

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State SW current next output SW E1 E2 E1 + E2 + 1,2 3, Combinational Circuit Traffic warning sign SW All off 1,2 on 1,2,3,4 on All on , SW 1,2 3,4 5 Cl E1 E2 E1 E2 SW E1 + = SW E1 E2 + SW E1 E2 E2 + = SW E1 E2 + SW E1 E2 1,2 = E1 + + SW E1 E2 3,4 = E1 + + SW E1 E2 5 = SW E1 E2 E1 + E2 + 1,2 3,4 5 E1 + E2 + E1 E2 SW Combinational Circuit

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a b c Next State Reversible counter modulo 5 a+ = abcI + bcI b+ = (c + ab) I + cI c+ = ab + bI + ab I a+ b+ c+ a b c I CL xx x x x x a b c I xx x x x 1 a b c I xx x x x 1 a b c I a+ = abcI + bcIb+ = (c + ab) I + cIc+ = ab + bI + ab I

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