Presentation on theme: "Boolean Algebra Variables: only 2 values (0,1)"— Presentation transcript:
1 Boolean Algebra Variables: only 2 values (0,1) Huntington’s (1804) axioms:1 1 = = 0a 0 = a + 1 = 1a a’ = a + a’ = 1a b = b a a + b = b + aa(b+c)=ab+ac a+bc=(a+b)(a+c)Verification by truth table:abc (a+b)c ac+bcApplication to electric switches (open - 0, closed - 1):aLc220V~bL = (a + b)c = ac + bcacL220V~bcL = ac + bcEvery logical function can be specified by truth table andimplemented as sum of product form,e.g. L = a’bc + ab’c + abc.
2 Combinational Circuits Output is direct function of inputsaa’NOTSwitch light L implemented by gatesL = a’bc + ab’c + abc sum of products.aba+ba b cLORababFunction presentation by Karnough mapevery product term has a field, and neighboringfields differ by only one variable.Example (three input variables):L = abc + ab’c + a’bc= abc + ab’c + abc + a’bc= ac(b + b’) + bc(a + a’)= ac + bc= (a + b)cba11caa+b1bLcL
3 Decoders and Multiplexers Decoder has n inputs and 2n outputs:ABBAMux determines which input will connect to output:A B C DA B C D1111S[1:0]2S1OUTOUT
4 Binary Adder Design a0 a3 a2 a1 b3 b2 b1 b0 c3 c2 c1 c0 c4 s3 s2 s1 s0 cocia b ciscoTruth Tablea b ci s coKarnough mapsabciabci11111111s = ab ci +ab ci’+a’b’ ci +a’b’ ci’=(ab + a’b’)ci +(ab + a’b’)ci’ =(a + b’) + ci =a + b’ + cico = ab + aci + bci
5 Programmable Logic Arrays PLA Any logical function can be implemented by two levels circuits: ANDs and ORs.ABCXY
6 Design of the RS flip-flop cbapx1a:a:b:b:abCCpca b pstablexcbax1p = a + b’cb’pcaabp’abpptime
7 Registers One bit register = memory cell WE = Clock pulse in bit gate out bitEight bit registerb7b6b5b4b3b2b1b0WE
8 The Concept of Memory WE N address lines (bus) address space = 2N Memory as array of registers: address space and addressabilityaddress decodermemory 0WEmemory 1memory 2N addresslines (bus)addressspace = 2Nmemory 3memory 4memory 5memory 6memory 7M data lines (bus)
9 Memory details address word select word WE input bits write enable Decoder asserts one of the word select lines, based on address.Word select activates one of the output AND gates, which drives the selected data to the output OR gate. (For a read, this is basically a MUX -- decoder ANDed with signals, results ORed together.)When writing, the only WE bits for the proper word are asserted (based on decoder again).output bits
10 Design of the JK flip-flop masterslaveJABQQ’ABKCLB closesA closesA opensmaster acceptsB opensslave acceptsAt no time the path between inputs JK and outputs QQ’ is closed.
11 Synchronous Sequential Circuit OutputInputCCNextstatePresentstateABclock* Output is a function of Input and Present state.* Next state is a function of Input and Present state.* Present state is delayed Next state.
12 Traffic warning sign All off 1,2 on 00 01 10 11 0,1 1 1 2 3 4 5 1,2,3,4000110110,111,212345SWSW3,4CombinationalCircuit5SWE1E1+E2E2+StateSW current next outputSW E1 E2 E1+ E2+ 1,2 3,4 5ClE1E21,23,45E1+E2+E1E2SWE1+ = SW E1’ E2 + SW E1 E2’E2+ = SW E1’ E2’ + SW E1 E2’1,2 = E SW E1 E23,4 = E SW E1 E25 = SW E1 E2CombinationalCircuit
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