4Overview Synchronous Sequential Logic Design Procedure Introduction to sequential circuitsTypes of sequential circuitsStorage elementsLatchesFlip-flopsSequential circuit analysisState tablesDesign Procedure
5Introduction to Sequential Circuits InputsOutputsCombina-tionalLogicA Sequential circuit contains:Storage elements: Latches or Flip-FlopsCombinational Logic:Implements a multiple-output switching functionInputs are signals from the outside.Outputs are signals to the outside.Other inputs, State or Present State, are signals from storage elements.The remaining outputs, Next State are inputs to storage elements.Storage ElementsStateNextState
6Introduction to Sequential Circuits InputsOutputsCombina-tionalLogicCombinatorial LogicNext state function Next State = f(Inputs, State)Output function (Mealy) Outputs = g(Inputs, State)Output function (Moore) Outputs = h(State)Output function type depends on specification and affects the design significantlyStorage ElementsStateNextState
7Types of Sequential Circuits Depends on the times at which:storage elements observe their inputs, andstorage elements change their stateSynchronousBehavior defined from knowledge of its signals at discrete instances of timeStorage elements observe inputs and can change state only in relation to a timing signal (clock pulses from a clock)AsynchronousBehavior defined from knowledge of inputs an any instant of time and the order in continuous time in which inputs changeIf clock just regarded as another input, all circuits are asynchronous!Nevertheless, the synchronous abstraction makes complex designs tractable!
8Basic (NAND) S – R Latch“Cross-Coupling” two NAND gates gives the S -R Latch:Which has the time sequence behavior:S = 0, R = 0 is forbidden as input patternS (set)QQR (reset)TimeRSQComment1?Stored state unknown“Set” Q to 1Now Q “remembers” 1“Reset” Q to 0111Now Q “remembers” 011Both go high11??Unstable!
9Basic (NOR) S – R LatchCross-coupling two NOR gates gives the S – R Latch:Which has the time sequence behavior:S (set)R (reset)QRSQComment?Stored state unknown1“Set” Q to 1Now Q “remembers” 1“Reset” Q to 0Now Q “remembers” 0Both go lowUnstable!Time
10Clocked S - R LatchAdding two NAND gates to the basic S - R NAND latch gives the clocked S – R latch:Has a time sequence behavior similar to the basic S- R latch except that the S and R inputs are only observed when the line C is high.C means “control” or “clock”.SRQC
11Clocked S-R Latch (continued) The Clocked S-R Latch can be described by a table:The table describes what happens after the clock [at time (t+1)] based on:current inputs (S,R) andcurrent state Q(t).SRQC
12D Latch Adding an inverter to the S-R Latch, gives the D Latch: Note that there are no “indeterminate” states!DQCQDQ(t+1)CommentNo change1Set QClear QNo ChangeCDQ
13Flip-Flops The latch timing problem Master-slave flip-flop Edge-triggered flip-flopStandard symbols for storage elementsDirect inputs to flip-flops
14Storage Elements Flip Flops In a sequential circuit the changes should take place with clock transitions and not with levels.
15S-R Master-Slave Flip-Flop Consists of two clocked S-R latches in series with the clock on the second latch invertedThe input is observed by the first latch with C = 1The output is changed by the second latch with C = 0The path from input to output is broken by the difference in clocking values (C = 1 and C = 0).The behavior demonstrated by the example with D driven by Y given previously is prevented since the clock must change from 1 to 0 before a change in Y based on D can occur.CSRQ
16Flip-Flop Solution Use edge-triggering instead of master- slave An edge-triggered flip-flop ignores the pulse while it is at a constant level and triggers only during a transition of the clock signalEdge-triggered flip-flops can be built directly at the electronic circuit level, orA master-slave D flip-flop which also exhibits edge-triggered behavior can be used.
17Edge-Triggered D Flip-Flop The edge-triggered D flip-flop is the same as the master- slave D flip-flopIt can be formed by:Replacing the first clocked S-R latch with a clocked D latch orAdding a D input and inverter to a master-slave S-R flip-flopThe change of the D flip-flop output is associated with the negative edge at the end of the pulseIt is called a negative-edge triggered flip-flopCSRQD
18Edge-Triggered D Flip-Flop The edge-triggered flip-flop consists of two latches: master and slave.
19JK Flip-FlopOther types of flip-flops may be constructed from D flip-flop. Two other types less commonly used are JK and T flip flops.
23Sequential Circuit Analysis General ModelCurrent State at time (t) is stored in an array of flip-flops. Next State at time (t+1) is a Boolean function of State and Inputs.Outputs at time (t) are a Boolean function of State(t) &(sometimes)Inputs (t).InputsCombina-tionalLogicOutputsStorage ElementsCLKStateNextState
24Example x y Input: x(t) Output: y(t) State: ((A(t), B(t)) What is the Output Function?What is the Next State Function?ACDQyxBCP
25State Table Characteristics State table – a multiple variable table with the following four sections:Present State – the values of the state variables for each allowed state.Input – the input combinations allowed.Next-state – the value of the state at time (t+1) based on the present state and the input.Output – the value of the output as a function of the present state and (sometimes) the input.From the viewpoint of a truth table:the inputs are Input, Present Stateand the outputs are Output, Next State
26Example: State TableThe state table can be filled in using the next state and output equations: A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) =A (t)x(t) y(t) =x (t)(B(t) + A(t))Present StateInputNext StateOutputA(t) B(t)x(t)A(t+1) B(t+1)y(t)1
27Example: Alternate State Table 2-dimensional table that matches well to a K- map. Present state rows and input columns in Gray code order.A(t+1) = A(t)x(t) + B(t)x(t)B(t+1) =A (t)x(t)y(t) =x (t)(B(t) + A(t))PresentStateNext Statex(t)= x(t)=1Outputx(t)=0 x(t)=1A(t) B(t)A(t+1)B(t+1) A(t+1)B(t+1)y(t) y(t)0 00 11 01 1
29Analysis with JK Flip Flops Determine flip-flop input equations in terms of present state and inputs.For each JKFF determine J=f(Q(t),x(t)) and K=g(Q(t),x(t))Using the flip-flop characteristic table determine the next state values in the state table.Substitute equations for J and K into Q(t+1)=JQ’+K’Q to calculate the values of next-states
33Excitation TablesInput equations for D-FF is obtained directly from next stateFor JK and T FFs FF input equations cannot be obtained easily from state table.A table that lists the inputs for a given change of state is needed.It is called excitation table
38Shift RegisterA register capable of shifting the binary information held in each cell to its neighboring cell, is called a shift register.Serial input is shifted to right with each clock pulse.After four clock pulses serial input appearsat the Serial output.
39Serial TransferA digital system operates at serial mode: information transferred and manipulated one bit at a time.Serial transfers take place with the system clock.In the next clock contents of shift register A is transferred to shift register B.
42Serial AdderTwo binary numbers to be added are stored in two shift registers A and B.The shift registers are shifted right starting with least significant bit, the bits are added by the full adder and carry is stored in a D flip-flop.When the addition is completed the sum is in regiater A.Serial adder will require n clock pulses for adding n-bit numbers. A parallel adder can perform the n-bit addition in one clock pulse period.However a parallel adder will have n full adders.
44CountersA register that goes through a prescribed sequence of states upon application of input pulses is called a counter.A counter that follows binary number sequence is called a binary countern-bit binary counter consists of n flip-flops and count from 0 to 2^n-1.
45Ripple CountersTwo categories: ripple counters and synchronous countersIn a ripple counter the clock input of flip- flops is connected to output of other flip flopsRipple counters do not have a common clock (not synchronous circuit)Synchronous counters have common clock connected to clock input of flip-flops
54bibliographyCharles H. Roth- Jr., Fundamentals of logic design, Thomson Asia,5th edition (CH1,CH2,CH3,CH4,CH5,CH6,CH7,CH9,CH11, CH12)M. Morris Mano, Digital Logic and Computer Design, Prentice Hall of IndiaFloyd, Digital Fundamentals, Universal Book Stall, 3rd Edition,1986Morris Mano, Digital Design, Prentice Hall of India, 2nd Edition 1991Bigell & Donovan, Digital Electronics, Thomson Asia Pvt. Ltd., 4th Edition
55Review questionsState the difference between combinational circuits and sequential circuits?What do you mean by Latches?Give the difference between latches and flip flops?Define Flipflops?List the design procedures for designing a sequential circuit?State the operation of S-R flipflop?State the operation of T-fliflop?State the features of clocked T flipflop?
56Review questionsGive the characteristics equation for S-R , T,J-K and D-flipflop?What is a counter?What is a buffer register?List the types of shift register?How do you convert JR flipflop into D flipflop?How do you convert T flipflop into D- flipflop?Give the counter applications?