1. P.Rajasekar & C.M.T.Karthigeyan Asst.Professor SRM University, Kattankulathur 8/22/2011 School of Computing, Department of IT 1

2. The contents of the slides are solely for the purpose of teaching students at SRM University. All copyrights and Trademarks of organizations/persons apply even if not specified explicitly. 8/22/2011 School of Computing, Department of IT 2

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4. Simple computer architecture decomposed into: Datapath for performing operations Control unit for controlling datapath operations A datapath is specified by: A set of registers The microoperations performed on the data stored in the registers A control interface 4

5. Guiding principles for basic datapaths: The set of registers Collection of individual registers A set of registers with common access resources called a register file A combination of the above Microoperation implementation One or more shared resources for implementing microoperations Buses - shared transfer paths Arithmetic-Logic Unit (ALU) - shared resource for implementing arithmetic and logic microoperations Shifter - shared resource for implementing shift microoperations 5

6. 6 Processor registers & ALU connected through common buses

7. Registers in a processor unit can be enclosed within a small memory unit A small memory when included in a processor unit is scratchpad memory 7

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9. It is a multi operation, combinational logic digital function Perform a set of basic arithmetic operations and a set of logic operations Next slide shows the block diagram of a 4 bit ALU 9

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11. Basic component of the arithmetic section of an ALU is a parallel adder Parallel adder is constructed with a number of full adder circuits connected in cascade 11

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16. A status register or flag register (also: condition code register, program status word, PSW, etc.) is a collection of flag bits for a processor 16

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18. 18 FlagNameDescription ZZero flag Indicates that the result of a arithmetic or logical operation (or, sometimes, a load) was zero. CCarry flag Enables numbers larger than a single word to be added/subtracted by carrying a binary digit from a less significant word to the least significant bit of a more significant word as needed. It is also used to extend bit shifts and rotates in a similar manner on many processors (sometimes done via a dedicated X flag). S / N Sign flag / Negative flag Indicates that the result of a mathematical operation is negative. In some processors, the N and S flags are distinct with different meanings and usage: One indicates whether the last result was negative whereas the other indicates whether a subtraction or addition has taken place. V / O / W Overflow flag Indicates that the signed result of an operation is too large to fit in the register width using twos complement representation. PParity flag Indicates whether the number of set bits of the last result is odd or even.

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20. 20 Register A Combinational circuit Data inputs B Control variables

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23. Design process is divided into six phases decomposition of the digital computer into registers which specify the general configuration of the system spec. of computer instructions formulation of a timing and control network listing of register-transfer operations needed to execute all computer instructions design of the processor section design of the control section 23

24. Memory address (MAR) & Buffer Registers Used to address specific memory locations It is loaded from PC Program counter (PC) Hold the address of the next instruction to be read from memory Accumulator Register (A) Processor register that operates on data previously stored in memory Instruction Register (IR) Holds the operation code bits of the current instruction 24

25. Sequence Register This produces the timing signals for the computer E, F and S Flip flops Each FF is a one bit register E FF is an extension of A register(shifting) F FF distinguishes fetch and execute cycles S FF – start(1) /stop(0) Input and Output Registers KB or a printer 25

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28. The numerical representation of instructions, combined with coding rules and conventions is called an instruction format. Opcodes: numerical codes for control operations Operands: numerical codes for data objects or their addresses. Opcodes are few (10-100) Few bits sufficient. Best if format/length/positions of opcodes fixed in instruction format. Operand addresses could be as much as 2^32. Need registers and addressing modes to make it compact 28

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30. 30 AND to A ADD to A STORE in A Increment and skip if Zero(ISZ) Branch Unconditionally(BUN) Branch to Subroutine(BSB)

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33. Charles H. Roth- Jr., Fundamentals of logic design, Thomson Asia,5th edition-2004 (CH1,CH2,CH3,CH4,CH5,CH6,CH7,CH9,CH11, CH12) M. Morris Mano, Digital Logic and Computer Design, Prentice Hall of India Floyd, Digital Fundamentals, Universal Book Stall, 3rd Edition,1986 Morris Mano, Digital Design, Prentice Hall of India, 2nd Edition 1991 Bigell & Donovan, Digital Electronics, Thomson Asia Pvt. Ltd., 4th Edition 8/22/2011 School of Computing, Department of IT 33

34. 1. What is the purpose of ALU? 2. Draw the logic diagram of logic circuit. 3. What are condition code bits? 4. What is the purpose of MBR? 5. What is the purpose of Program Counter? 6. What is the purpose of Sequence Register? 7. What is the purpose of Instruction Register? 8/22/2011 School of Computing, Department of IT 34

35. 8. What are all the types of computer instructions? 9. Give any two memory reference instructions. 10. Give any two register reference instructions. 11. Give any two input output instructions 12. What is the purpose of BUN and BSB instructions? 13. What is the purpose of CLA? 14. What is the purpose of MAR? 8/22/2011 School of Computing, Department of IT 35