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Chapter 10 Flip-Flops and Registers 1. Objectives You should be able to: Explain the internal circuit operation of S-R and gated S-R flip-flops. Explain.

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Presentation on theme: "Chapter 10 Flip-Flops and Registers 1. Objectives You should be able to: Explain the internal circuit operation of S-R and gated S-R flip-flops. Explain."— Presentation transcript:

1 Chapter 10 Flip-Flops and Registers 1

2 Objectives You should be able to: Explain the internal circuit operation of S-R and gated S-R flip-flops. Explain the internal circuit operation of S-R and gated S-R flip-flops. Compare the operation of D latches and D flip-flops by using timing diagrams. Compare the operation of D latches and D flip-flops by using timing diagrams. Describe the difference between pulse-triggered and edge-triggered flip-flops. Describe the difference between pulse-triggered and edge-triggered flip-flops. 2

3 Objectives (Continued) Explain the theory of operation of master-slave devices. Explain the theory of operation of master-slave devices. Connect IC J-K flip-flops as toggle and D flip-flops. Connect IC J-K flip-flops as toggle and D flip-flops. Use timing diagrams to illustrate the synchronous and asynchronous operation of J-K flip-flops. Use timing diagrams to illustrate the synchronous and asynchronous operation of J-K flip-flops. 3

4 S-R Flip-Flop Data storage circuit Data storage circuit Cross-coupled NOR scheme Cross-coupled NOR scheme Asynchronous set and reset Asynchronous set and reset 4

5 S-R Flip-Flop Function table Function table 5

6 S-R Flip-Flop Data storage circuit Data storage circuit Cross-coupled NAND scheme Cross-coupled NAND scheme 6

7 S-R Flip-Flop Function table Function table 7

8 S-R Flip-Flop Both true and complemented Q outputs Both true and complemented Q outputs Symbols for a S-R FF Symbols for a S-R FF 8

9 S-R Flip-Flop Timing Analysis 9

10 S-R Flip-Flop Application Storage register to remember time of day when a temperature limit switch goes high. Storage register to remember time of day when a temperature limit switch goes high. 11

11 Gated S-R Flip-Flop Asynchronous – output responds immediately to input Asynchronous – output responds immediately to input Synchronous – output responds in step with a control input Synchronous – output responds in step with a control input 13

12 Gated S-R Flip-Flop Function table and symbol Function table and symbol 14

13 Gated D Flip-Flop Data flip-flop with example inputs and outputs Data flip-flop with example inputs and outputs 15

14 Discussion Point How will the complement of an output differ from the output? How will the complement of an output differ from the output? Explain the difference between synchronous and asynchronous inputs. Explain the difference between synchronous and asynchronous inputs. 16

15 7475 Integrated Circuit D Latch Four transparent D latches Four transparent D latches Bistable latch, logic symbol and pin configuration Bistable latch, logic symbol and pin configuration 17

16 7474 Integrated Circuit D Flip-Flop Positive edge-triggered device Positive edge-triggered device Transitions of output occur at the edge of input trigger pulse Transitions of output occur at the edge of input trigger pulse Clock signal usually used as trigger pulse Clock signal usually used as trigger pulse 19

17 7474 Integrated Circuit D Flip-Flop Logic symbol and pin configuration 20

18 Integrated Circuit D Flip-Flop Positive edge-detection circuit Positive edge-detection circuit 21

19 Integrated Circuit D Flip-Flop Synchronous inputs Synchronous inputs D (Data) D (Data) C p (Clock) C p (Clock) Asynchronous inputs Asynchronous inputs S D (Set) S D (Set) R D (Reset) R D (Reset) Function Table (see Table 10-4 in the text) Function Table (see Table 10-4 in the text) Setup Time - time D must be stable before transition of C p Setup Time - time D must be stable before transition of C p 22

20 Master-Slave J-K Flip-Flop Toggle mode Toggle mode Switches to opposite state at active clock edge Switches to opposite state at active clock edge Master-slave Master-slave Master receives data while input trigger is HIGH Master receives data while input trigger is HIGH Slave receives data from master and outputs it when clock goes LOW Slave receives data from master and outputs it when clock goes LOW 24

21 Master-Slave J-K Flip-Flop Function Table Function Table 25

22 Master-Slave J-K Flip-Flop Equivalent circuit and logic symbol Equivalent circuit and logic symbol 26

23 Master-Slave J-K Flip-Flop Pulse-triggered (level-triggered) Pulse-triggered (level-triggered) Input data is read during entire time clock pulse is at a HIGH level Input data is read during entire time clock pulse is at a HIGH level Ones catching Ones catching 27

24 Edge-Triggered J-K Flip-Flop Accepts data on the J and K inputs only at the active clock edge Accepts data on the J and K inputs only at the active clock edge Symbols for positive and negative edge triggered J-K FFs Symbols for positive and negative edge triggered J-K FFs 28

25 Edge-Triggered J-K Flip-Flop Function Table Function Table 29

26 Discussion Point How are pulse triggered (level triggered) devices different from edge triggered devices? How are pulse triggered (level triggered) devices different from edge triggered devices? What is ones catching? What is ones catching? Identify the synchronous and asynchronous inputs on a JK flip-flop logic symbol Identify the synchronous and asynchronous inputs on a JK flip-flop logic symbol 30

27 Integrated Circuit J-K Flip-Flop 7476 - master-slave 7476 - master-slave 74LS76 - negative edge- triggered 74LS76 - negative edge- triggered Logic symbol and pin configuration Logic symbol and pin configuration 31

28 Integrated Circuit J-K Flip-Flop To form a D flip-flop add an inverter To form a D flip-flop add an inverter 33

29 Integrated Circuit J-K Flip-Flop To form a toggle flip-flop tie inputs HIGH To form a toggle flip-flop tie inputs HIGH 34

30 Using an Octal D Flip-Flop in a Microcontroller Application Octal ICs - eight on a chip Octal ICs - eight on a chip 8-bit register 8-bit register 74HCT273 logic diagram 74HCT273 logic diagram 35

31 Using an Octal D Flip-Flop in a Microcontroller Application The 74HCT273 as an update and hold register The 74HCT273 as an update and hold register Figure 10-45 36

32 Summary The S-R flip-flop is a single-bit data storage circuit that can be constructed using basic gates. The S-R flip-flop is a single-bit data storage circuit that can be constructed using basic gates. Adding gate enable circuitry to the S-R flip-flop makes it synchronous. This means that it will operate only under the control of a clock or enable signal. Adding gate enable circuitry to the S-R flip-flop makes it synchronous. This means that it will operate only under the control of a clock or enable signal. 37

33 Summary The D flip-flop operates similar to the S-R, except it has only a single data input, D. The D flip-flop operates similar to the S-R, except it has only a single data input, D. The 7475 is an integrated-circuit D latch. The output (Q) follows D while the enable (E) is HIGH. When E goes LOW, Q remains latched. The 7475 is an integrated-circuit D latch. The output (Q) follows D while the enable (E) is HIGH. When E goes LOW, Q remains latched. 38

34 Summary The 7474 is an integrated-circuit D flip-flop. It has two synchronous inputs, D and C p, and two asynchronous inputs, S D and R D. Q changes to the level of D at the positive edge of C p. Q responds immediately to the asynchronous inputs regardless of the synchronous operations. The 7474 is an integrated-circuit D flip-flop. It has two synchronous inputs, D and C p, and two asynchronous inputs, S D and R D. Q changes to the level of D at the positive edge of C p. Q responds immediately to the asynchronous inputs regardless of the synchronous operations. 39

35 Summary The J-K flip-flop differs from the S-R flip- flop because it can also perform a toggle operation. Toggling means that Q flips to its opposite state. The J-K flip-flop differs from the S-R flip- flop because it can also perform a toggle operation. Toggling means that Q flips to its opposite state. The master-slave J-K slip-flop consists of two latches: a master that receives data while the clock trigger is HIGH, and a slave that receives data from the master and outputs it to Q when the clock goes LOW. The master-slave J-K slip-flop consists of two latches: a master that receives data while the clock trigger is HIGH, and a slave that receives data from the master and outputs it to Q when the clock goes LOW. 40

36 Summary The 74LS76 is an edge-triggered J-K flip-flop IC. It has synchronous and asynchronous inputs. The 7476 is similar, except it is a pulse-triggered master-slave type. The 74LS76 is an edge-triggered J-K flip-flop IC. It has synchronous and asynchronous inputs. The 7476 is similar, except it is a pulse-triggered master-slave type. The 74HCT273 is an example of an octal D flip-flop. It has eight D flip-flops in a single IC package, making it ideal for microprocessor applications. The 74HCT273 is an example of an octal D flip-flop. It has eight D flip-flops in a single IC package, making it ideal for microprocessor applications. 41


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