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Floyd, Digital Fundamentals, 10 th ed EET 1131 Unit 6 Exclusive-OR and Exclusive-NOR Gates Read Kleitz, Chapter 6. Do Unit 6 e-Lesson. Homework #6 and.

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Presentation on theme: "Floyd, Digital Fundamentals, 10 th ed EET 1131 Unit 6 Exclusive-OR and Exclusive-NOR Gates Read Kleitz, Chapter 6. Do Unit 6 e-Lesson. Homework #6 and."— Presentation transcript:

1 Floyd, Digital Fundamentals, 10 th ed EET 1131 Unit 6 Exclusive-OR and Exclusive-NOR Gates Read Kleitz, Chapter 6. Do Unit 6 e-Lesson. Homework #6 and Lab #6 due next week. Quiz next week.

2 © 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed The XOR gate produces a HIGH output only when the inputs are at opposite logic levels. The truth table is The XOR Gate A B XA B X The XOR operation is written as X = AB + AB. Alternatively, it can be written with a circled plus sign between the variables as X = A + B.

3 © 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Example waveforms: A X Notice that the XOR gate will produce a HIGH only when exactly one input is HIGH. The XOR Gate B A B XA B X

4 © 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Some common gate configurations are shown. Fixed Function Logic

5 © 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed The XNOR gate produces a HIGH output only when the inputs are at the same logic level. The truth table is The XNOR Gate A B XA B X The XNOR operation can be written as X = AB + AB or as X = A + B.

6 © 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Example waveforms: A X Notice that the XNOR gate will produce a HIGH when both inputs are the same. This makes it useful for comparison functions. The XNOR Gate B A B XA B X

7 Floyd, Digital Fundamentals, 10 th ed Applications of XOR and XNOR Gates Three common applications: 1. Comparators 2. Controlled inverters 3. Parity generation and checking

8 Floyd, Digital Fundamentals, 10 th ed Convention for Multi-Bit Strings When dealing with multi-bit binary strings, we use subscripts to refer to the individual bits in the string. The least significant bit (LSB) always gets the smallest subscript, which may be either 1 or 0. Example: In a four-bit string A, the bits may be labeled either A 4 A 3 A 2 A 1 or A 3 A 2 A 1 A 0

9 Floyd, Digital Fundamentals, 10 th ed Application #1: Comparator A comparator compares two string of bits to see whether they are equal to each other: Example: if string A = 0101 and string B = 0100, then A B. Next slide shows how to build a 4-bit comparator from XNOR gates.

10 Floyd, Digital Fundamentals, 10 th ed Comparator Circuit (Books Fig. 6-14)

11 Floyd, Digital Fundamentals, 10 th ed Application #2: Controlled Inverter A controlled inverter takes an input string and, depending on the logic level on a control line, either Leaves the string unchanged or Inverts each bit in the string Next slide shows how to build an 8-bit controlled inverter from XOR gates.

12 Floyd, Digital Fundamentals, 10 th ed Controlled Inverter (Books Fig. 6-15)

13 © 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Application #3: Parity Checking Parity checking is a method of error detection for simple transmission errors involving one bit. A parity bit is an extra bit attached to a group of bits to force the total number of 1s to be either even (even parity) or odd (odd parity). The ASCII character for a is and for A is What is the correct bit to append to make both of these have odd parity? The ASCII a has an odd number of bits that are equal to 1; therefore the parity bit is 0. The ASCII A has an even number of bits that are equal to 1; therefore the parity bit is 1.

14 Parity Generators To implement parity checking, we need circuitry on the sending end that generates the parity bit for each group of bits being sent. This circuitry is called a parity generator. Next slide shows how to build 4-bit even or odd parity generators.

15 Parity Generators (Books Fig. 6-9)

16 Parity Checkers On the receiving end, we need circuitry that checks the data bits and parity bit as theyre received to decide whether an error has occurred during transmission. This circuitry is called a parity checker. Next slide shows how to build a 4- bit-plus-parity even parity checker.

17 Parity Checker (Books Fig. 6-11)

18 A Parity Generator/Checker Chip Nine -bit Parity Generator/Checker Most chips weve studied have been SSI (small-scale integration) chips containing fewer than 10 gates that are not connected to each other. The is an MSI (medium-scale integration chip). Instead of containing a few disconnected gates, it contains about 45 gates connected internally on the chip to perform a specific function.

19 Parity System (Books Fig. 6-13)

20 © 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Parity Generator/Checker Chip The can be used to generate a parity bit or to check an incoming data stream for even or odd parity. Checker: The can test codes with up to 9 bits. The even output will be HIGH if the data lines have even parity; otherwise it will be LOW. Likewise, the odd output will be HIGH if the data lines have odd parity; otherwise it will be LOW. Generator: To generate even parity, the parity bit is taken from the odd parity output. To generate odd parity, the output is taken from the even parity output Data inputs Even Odd

21 Printing from Our Oscilloscopes You can print the oscilloscope screen by pressing the PRINT button. Theres a delay of about 40 seconds before the page will print, so be patient. Only one oscilloscope can print at a time, or else the printer gets confused and prints hundreds of pages. Please shout Printing! before you press the PRINT button, and make sure that you dont print while someone else is waiting for their page to print.


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