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©2004 Brooks/Cole FIGURES FOR CHAPTER 16 SEQUENTIAL CIRCUIT DESIGN Click the mouse to move to the next page. Use the ESC key to exit this chapter. This.

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Presentation on theme: "©2004 Brooks/Cole FIGURES FOR CHAPTER 16 SEQUENTIAL CIRCUIT DESIGN Click the mouse to move to the next page. Use the ESC key to exit this chapter. This."— Presentation transcript:

1 ©2004 Brooks/Cole FIGURES FOR CHAPTER 16 SEQUENTIAL CIRCUIT DESIGN Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter in the book includes: Objectives Study Guide 16.1Summary of Design Procedure for Sequential Circuits 16.2Design Example--Code Converter 16.3Design of Iterative Circuits 16.4Design of Sequential Circuits Using ROMs and PLAs 16.5Sequential Circuit Design Using CPLDs 16.6Sequential Circuit Design Using FPGAs 16.7Simulation and Testing of Sequential Circuits 16.8Overview of Computer-Aided Design Design Problems Additional Problems

2 ©2004 Brooks/Cole Table 16-1.

3 ©2004 Brooks/Cole Table State Table for Code Converter

4 ©2004 Brooks/Cole Table Reduced State Table for Code Converter

5 ©2004 Brooks/Cole Figure 16-1: State Graph for Code Converter

6 ©2004 Brooks/Cole Figure 16-2: Assignment Map for Flip Flops (b) Transition table ABCDEHM-ABCDEHM-

7 ©2004 Brooks/Cole Figure 16-3: Karnaugh Maps for Code Converter Design

8 ©2004 Brooks/Cole Figure 16-4: Code Converter Circuit

9 ©2004 Brooks/Cole Figure 16-5: Unilateral Iterative Circuit

10 ©2004 Brooks/Cole Figure 16-6: Form of Iterative Circuit for Comparing Binary Numbers

11 ©2004 Brooks/Cole Table 16-4 State Table for Comparator

12 ©2004 Brooks/Cole Table 16-5 Transition Table for Comparator

13 ©2004 Brooks/Cole Figure 16-7: Typical Cell for Comparator

14 ©2004 Brooks/Cole Figure 16-8: Output Circuit for Comparator

15 ©2004 Brooks/Cole Figure 16-9: Sequential Comparator for Binary Numbers

16 ©2004 Brooks/Cole Table 16-6a

17 ©2004 Brooks/Cole Table 16-6b

18 ©2004 Brooks/Cole Table 16-6c Truth Table

19 ©2004 Brooks/Cole Figure 16-10: Realization of Table 16.6(a) Using a ROM

20 ©2004 Brooks/Cole Table 16-7

21 ©2004 Brooks/Cole Figure 16-11: Segment of Sequential PAL

22 ©2004 Brooks/Cole Figure 16-12: CoolRunner-II Architecture (Figure based on figures and text owned by Xilinx, Inc., Courtesy of Xilinx, Inc. © Xilinx, Inc All rights reserved.)

23 ©2004 Brooks/Cole Figure 16-13: CoolRunner-II Macrocell (Figure based on figures and text owned by Xilinx, Inc., Courtesy of Xilinx, Inc. © Xilinx, Inc All rights reserved.)

24 ©2004 Brooks/Cole Figure 16-14: CPLD Implementation of a Mealy Machine

25 ©2004 Brooks/Cole Figure 16-15: CPLD Implementation of a Shift Register

26 ©2004 Brooks/Cole Figure 16-16: CPLD Implementation of a Parallel Adder with Accumulator

27 ©2004 Brooks/Cole Figure 16-17: Xilinx Virtex/Spartan II CLB (Figure based on figures and text owned by Xilinx, Inc., Courtesy of Xilinx, Inc. © Xilinx, Inc All rights reserved.)

28 ©2004 Brooks/Cole Figure 16-18: FPGA Implementation of a Mealy Machine

29 ©2004 Brooks/Cole Figure 16-19: FPGA Implementation of a Shift Register

30 ©2004 Brooks/Cole Figure 16-20: FPGA Implementation of a Parallel Adder with Accumulator

31 ©2004 Brooks/Cole Figure 16-21: Simulator Output for an Inverter

32 ©2004 Brooks/Cole Figure 16-22: Simulation Screen for Figure 13-7

33 ©2004 Brooks/Cole Figure 16-23

34 ©2004 Brooks/Cole Figure 16-24: Using a Shift Register to Generate Synchronized Inputs

35 ©2004 Brooks/Cole Figure 16-25

36 ©2004 Brooks/Cole Figure 16-26: Synchronizer with Two D Flip-Flops

37 ©2004 Brooks/Cole Figure 16-27


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