Presentation on theme: "Application Engineering and Design Services"— Presentation transcript:
1 Application Engineering and Design Services Laminate Based System in Package (SiP) Utilizing High Density Interconnect (HDI) Substrates in High Reliability ApplicationsRon NowakSenior Manager,Application Engineering and Design Services10 March 2011
2 What is SiP?....An Integrated Solution System in Package (SiP) delivers 10-20X reductions from current designsUp to 90% weight reductionsSignificantly lower power and improved electrical performanceHi-Reliability, Hi-Quality, Hi-PerformanceRemove layers of interconnectAddresses growing demand in:Unmanned systemsRadarSpace satellitesElectronic WarfareMedical ApplicationsResearch ApplicationsThe magic dust:Bare dieHDI substrates7 mm620mm2 PWB reduced to 30mm2
3 System in Package Overview Typically multiple bare die and SMT components on a HDI microelectronics substrate:Large and Small Bare Die placement & attachFlip chip die connectionsWirebond die connectionDual sided attachComponent substitutionSMT placement & attachDown to 0201’s, 01005’sCSP’s, SOIC’s, PLCC’s, SOJ’sConnections to next level assemblySMT pinned connectorsBall Grid ArrayHigh Density Interconnect Substrates: the secret sauce !Laser drilled through and microvias25 micron trace width and spaceThin, low loss, low dielectric constant materials
4 System in Package Overview 4/1/2017System in Package OverviewPackage SizeStandard JEDEC 13.0mm to 55.0mmCustom size and shape SiPsAssembly to Organic SubstratesFR4 and BT epoxyParticle filed epoxy build-upPTFE dielectricKapton flexPolyimideLCPCommon Product ParametricsLarge MCM/SiP packagesHybrid/double-sided assemblySingle chip module and device packagesTestShorts-opensJTAG/boundary scanFull functional test
5 System-in-Package Conversion Where we begin:Technical contact at the customerSi design: Bare die availabilityPreliminary BOM AnalysisInputBill of Materials & Approved Vendor ListOutputSmaller package & bare die recommendationsPreliminary Area StudyBoard design file & Electrical restraintsinitial conversion of PCB to substratecross section, dielectric and size estimatesInitial assembly layoutSubstrate design and assembly layoutElectrical, thermal and mechanical analysis
8 Laminate vs. Ceramic Reliability Comparisons 45mm body sizeProductMaterialTypical Substrate ThicknessDielectric ConstantLoss TangentComponent Level Reliability -55 to 125oCBoard Level Reliability0-100oCHTCC (solder columns)Glass Ceramic 111.0 mm8.1.00341000 cycles2,200 cycles to 1st failHyperBGA®PTFE0.47 mm2.7.003 (49% silica filled)10,000 cycles to noCoreEZ TMEpoxy/P-Aramid Fiber Core and particle filled Epoxy build up0.526 mm(8 layer)3.5.0225,000 cycles to 1st failPlastic solutions offer:High electrical performanceHigh reliability performanceWeight reductionSmaller x, y, z form factor
9 PTFE Substrate Chip Joining Measured flatness of 42.5mm laminate + stiffener subassembly exampleViewed from BGA side: Moiré topographic fringe contours at 8.33 microns / fringeRoom temperature, 20C Reflow temperature, 183C14.7 mm size chip bump region (in red) remained flat to within 17 microns
12 Packaging Attributes applied to SiP conversions Substrate features and advanced IC Assembly techniques enable bare die implementationAttributeStandard PCBHDISubstrateShrink opportunityThrough viaMechanicalLaserThrough via dia.200 microns50 microns4XThrough via capture pad diameter400 microns100 micronsLine Width75 microns25 microns3XSpace WidthSemiconductorsPackagedBare die or small package4X to 10XFlip Chip Bump3-4-3 CoreEZ ®
13 2011 Product Attribute Comparisons 4/1/20172011 Product Attribute ComparisonsAttributeStandard(Epoxy Glass or Polyimide)HDI: Dense(Particle Filled Epoxy)HDI: LCP(liquid crystal polymer)HDI: PTFE(PTFE)Line width75 microns25 microns37.5 micronsLine space33 micronsVia typemechanicallaserLaserVia diameter200 microns50 micronsStacked viasBuild up onlyIn 2010Capture pad diameter400 microns100 microns110 micronsSurface finishE-less Ni / I Au, ENEPIGSameSolder maskyesnoThickness<1mmmm0.5mmLayers10124, 6 in 1st article11100ui min. for Ni, 2ui min. for Au. Wirebond on CoreEZ and HyperBGA finish is ENIG
15 Physical Design content Physical Design ImplementationComponent Placement & RoutingPhysical & formal verificationSignal Integrity (SI) & Crosstalk analysisStatic Timing Analysis (STA)Multiple Supply Voltage (MSV)Leakage Current Reduction TechniquesClock & Supply Voltage GatingPower OptimizationDesign for Test to ensure testabilityDesign for Manufacturability to maximize production yields
16 Signal and Power Integrity Potential Work Items and Design Flow Typical Signal Integrity Workflow (varies by application)Customer defines SI specifications in the form of routing constraints by net such as:Z0 (SE, DP), Skew (Group / reference), Crosstalk / Isolation Freq), Rdc, Insertion / Return loss Freq), etc.EIT ensures that these specifications are met as follows:Pre-layout Design Guidelines:Define stackup, function by layer, recommended component placementDefine trace width (and spacing for DP) for Z0 requirementsTranslate electrical Skew requirements into physical lengthsDefine spacing and coupled length limitations for crosstalk controlDefine trace geometries to meet loss specificationPost-layout Verification:Extract parameters from design database using Ansoft toolsetHFSS, Q3D, SIWave
18 Evaluation of Materials Subjected to Various Radiation Levels Evaluated PTFE BGA (HyperBGA®) and Thin Core (CoreEZ ®) materials radiation responseRadiation Exposure: Co60 Gamma:Control32, 50, 100, 300, 500, 700, 1000 and 5000 krad TIDPTFE Materials evaluated: Rogers 2800, PPEResults: Many applications will be unaffected by radiationPPE has no measurable degradation to 5 MradRO2800 shows gradual loss of ductility with exposureThin Core Build Up Materials Considered: Thermount 55LM, Particle Filled Driclad Epoxy, PSR4000Results: No measurable change of mechanical properties through Mrad
19 Packaging performance after radiation exposure Ductility performance indicates package performance in thermal cyclingThin Core Build Up appears to be a good choice for Rad Hard and Strategic apps.materials show no ductility degradation with radiation levelPTFE appears to be best suited for Rad Tolerant applicationsPTFE ductility is higher then all other materials below 300K rad exposurePTFE predictably degrades significantly above 300Krad exposure levels
22 Packaging Electrical Comparisons Notes: * measured values ; Loop inductance: Entire package , all C4 pads and BGA's commoned. The above electrical characteristics are typical of each product. Variations of these parameters can be achieved for a specific design.
27 Typical CoreEZ® 10 Layer Cross-Section 4/1/2017Cu-filled stacked microviasSoldermaskPSR400015 µm thickFlip Chip BumpsGND / TOPBuild-up layer 1Build-up layer 2Build-up layer 3Driclad, 35/50 µmthickS1PWR / GNDS2Outer coreDielectric, Driclad35/50 µm thickPWR / GNDInner core135 µm thickEpoxy/P-AramidPWR / GNDTilted solder balls compensate for misregistration between die and substrate pads. We could adjust our compensation with a larger volume product.Core Cu12 µm thickS3PWR / GNDBuild-up Cu 1Build-up Cu 2Build-up Cu 312 µm thickS4GND / BOT3-4-3 Stack up (10 copper layers)Substrate thickness 0.7 mm
28 8 Layer X-Section Comparison CoreEZ® 2-4-2Standard Build-up 3-2-3Photographs are atsame magnification- Both packages use 50um blind vias- CoreEZ® core vias are 4x smaller- Enhanced high speed electrical performance
29 HDI With High Core Via Density 4/1/2017Dense Package InterconnectDense Core Via PitchDual Side Component MountingFine Line Width and SpacingEnhanced Z-axis connectivityThin Core, SiP um viaStandard Build-Up um via~9X Core Via Density
30 CoreEZ™ Typical X-Sections CoreEZ™ is available as a 1-4-1, , or cross sections1-4-1 = 2 full stripline signal planes, 4 pwr/gnd2-4-2 = 4 dual stripline signal planes, 4 pwr/gnd3-4-3 = 4 full stripline signal planes, 6 power/gnd4-4-4 = 4 full stripline signal planes, 8 pwr/gnd4 – 4 - 4
31 Embedded Passives in CoreEZ® ResistorsThin film resistor materialTicer TCR®ohms per squareResistor values from 5 ohm to 50 KohmResistor tolerances from 2 – 20%Laser trimming 2 – 5%Typical resistor areas0.2 – 15 mm2Block or Serpentine designsEight layer core 285 nF / in2
32 High Speed SERDES in CoreEZ® Simulation at 12.5 Gbps 300 mV43 psSimilar electrical performance as PTFEWithin 10% of PTFE jitter performance
34 Why LCP? Is “near” hermetic Low moisture absorption: 0.04% Halogen Free (lead free assembly being evaluated)Similar in electrical performance to PTFELow LossDk = 2.9Df =Very Lightweight1.4gm/cm3ThermoplasticThin and thick layer combinations in cross sections25um, 50 um and 100 um thicknessCapable of Radiation Hardened applicationsRogers ULTRALAM 3850, 3908Nippon Steel Espanex L
37 First level Assembly Overview 4/1/2017First level Assembly OverviewElectronic packaging development, fabrication and advanced assembly of complex flip chip and wire bond packagesKey differentiators:Flip Chip, Wirebonding and SMT on one packageBGA ballingLead-free assembly01005 component placement and assemblyAlternative pad finishesTeradyne Ultra FLEXVLSI platform functional testingLeading edge process development
38 First level Assembly-Wirebond 4/1/2017First level Assembly-WirebondWire Bond Expertise……Die-up and cavityBall bonding 25 micron diameter Au wire to 125 micron pitchPitches down to 57µm on 700+ wire packageProduction qualified for military applicationsDie attach: sizes to 16mm squareRibbon bonding packages and cards to 12”Al ribbon bonding availableCoplanarity measurementsDamming and glob top
39 Flip Chip Assembly Needs 4/1/2017Flip Chip Assembly NeedsFlip Chip ExpertiseSiGe, Si, GaAs die attachHi melt, eutectic, Sn cap C4, Pb-freeLow alpha Sn/Pb solderHigh I/O Flip Chip join down to 150µm pitchDie sizes placed to 25mm x 26mmFlux chemistries/dispensingVarious low & high modulus underfillsBGA attach down to 0.5mm pitch (eutectic, Pb-free)PGA attachThermal adhesiveHeat spreader, heat sink & lid attach100µm pitch solder dispenseSolder volume measurementsCSAM acoustic imaging inspectionX-ray inspectionPart labeling/marking: traceability
40 Assembly Engineering Support 4/1/2017Assembly Engineering SupportSupport OperationsPre/post assembly coplanarity measurementAcoustic microscopy for interfacial inspectionReal time X-ray for process monitorsIonic cleanliness measurementsWire pull and ball shearSolder repair/reworkCross section support failure analysisTraceability to the component levelFixturing and process developmentAIR-VAC Hot Air Rework ToolCan rework leaded, lead free,and high melt BGA’s, Micro BGA’s,and flip chip die.
42 Extreme SiP Miniturization example Original PCB 620 mm2Package Size30 mm diameter, 391 total components39 different part numbers, 231 components on 2 surfaces5 Bare DieFlip Chip FPGA, 15.95mm x 10.23mm, 2,440 I/OFlip Chip DSP, 4.68mm x 5.134mm, 225 um pitch, 261I/OFlip Chip Supply monitor, pitch = 114 um, 16 I/OFlip Chip DRAM, pitch = 121 um, 86 i/oFlip Chip Flash memory, pitch = 116 um, 77 I/O178 SMT Capacitors, 14 SMT resistors152 buried resistors imbedded in substrate1 SMT circular connector> 100 producedSiP CoreEZTM 30 mm2
43 Intravascular Ultrasound Catheter Sensor Package Single layer HDI FlexFlip Chip Ultrasound Transducer for Cathetersensor assembly rolled to 1.175mm diameter5 Flip Chip ASIC,.1mm thick, 31 I/O, 2.5mm x .5mm22 micron flip chip bumps on 70 micron die pad pitch1 PZT crystal12.5mm by 6.5 mm single layer flex circuit14 micron wide lines and space copper circuitry12.5 thick polyimide dielectricPrototype to productionOver 320,000 modules shippedFlip Chip Bumps200 µmTransducerASIC Die7 mm
44 Low Level Gamma Photon Detector Module 9 layer HyperBGA PTFE SubstrateBottom side CZT CrystalPassives on mini cardS. Steel StiffenerTop side Wirebonded ASIC50 micron UV laser drilled vias25 micron trace33 micron spaceHyper Substrate X-SectionSubstrate TopSubstrate BottomASICsiteCZTsite
45 Microelectronics Packaging Conclusion Enable System Miniaturization using SiP: Bare die, HDI Substrate Materials, Assembly Technology & ManufacturingCombining advanced flip chip & wirebond with maximum HDI plastic substratesDeliver maximum reliability and electrical performance for RF and High Bandwidth DigitalSystem Level Shrink for SWaPPWB redesigns into fully integrated System in Package24X system size reductions have been realizedLower cost next level assemblies (lower layer count PWB’s)Deliver the industry’s smallest packages combined withsuperior package reliability and robust electrical performance!
46 AcknowledgmentsThe author would like to thank CERN for their invitation to participate in the ACES Workshop in Geneva and also thank the CEO of Endicott Interconnect Technologies for his kind permission to present this paper.Ron NowakWeb site:
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