4 7.1 Single chip package (SCP) 7.2 Functions of a SCPs7.3 Types of SCPs7.4 Fundamentals of SCP7.5 Materials, Processes, Properties7.6 Characteristics of SCPs7.7 Summary and Future Trends
5 7.1 Single Chip Package SCP supports a single microelectronic device Electrical, thermal, chemical performance adequately servedWafer Diced Packaged Burnt-in TestedPackaged IC = (few to million) of transistorsExample of SCP –Intel’s ceramic pin grid array –generations of X86 familymicroprocessors
6 Active vs. Passive devices ACTIVE devicesMemory or microprocessorActive – device capable of modifying and enabling the information in accordance with the logical instruction set.PASSIVE devicesResistors, capacitors, inductorsDo not alter the transmitted signalServe to optimize the performance and functionChapter 11
7 Examples of SCPMore than one ACTIVE device multichip package (MCP) or multichip module (MCM)System designers - Combination of PASSIVE components, SCPs, MCM to meet application needs of the system.Examples of SCP for common applications:
8 7.2 Functions of a SCPs 7.1 Single chip package (SCP) 7.3 Types of SCPs7.4 Fundamentals of SCP7.5 Materials, Processes, Properties7.6 Characteristics of SCPs7.7 Summary and Future Trends
9 7.2 Functions of a SCPs Product life varies Primary function – enable the device/chipPerform its designed functions in a reliable mannerProduct life varies1-2 years or less – cell phones and microprocessors for PCs15-20 years – public exchange telecommunication switchesUp to 40 years – military and aerospace applicationsEVERY single chip package MUST perform 6 functions:Signal transmission and power distribution TO and FROM the ICSignal transmission and power distribution BETWEEN the package device and other components.Enable device to be ATTACHED to the next level of packagingAllow for effective DISSIPATION OF HEAT generated by the packageProvide adequate PROTECTION of the deviceAct as SPACE TRANSFORMER between the fine pitch grid and the PWB pitch gridSingle chip package needs to deliver the best possible performance at the lowest possible cost.
10 7.3 Types of SCPs 7.1 Single chip package (SCP) 7.2 Functions of a SCPs7.3 Types of SCPs7.4 Fundamentals of SCP7.5 Materials, Processes, Properties7.6 Characteristics of SCPs7.7 Summary and Future trends
11 7.3 Types of SCPs Single chip packages classified into three types: PTH (pin-through-hole)SMT (surface mount technology)SMT-Area Array
12 Microprocessor evolution during last three decades IBM (CISC – complex instruction set computing)Apple (RISC – reduced instruction set computing)Ceramic Pin-Grid-Arrays (PGAs) used SCP since 1982Ease of pluggability and removal for IC repairProven reliabilityArea array connectionsCompatible PWB availabilityPlastic (PGAs) replaced ceramicRecently, build-up or high-density Ball-Grid-Array (BGA)Lower costHigher electrical performance
13 Table - Types of single chip packages, I/O, pitches and volumes In memory – plastic packages and lower pin count higher volumesHigher priced ceramics packages, high pin count lower volumesBGA emerges as dominant in futureJoint Electronic Device Engineering Council – establishes the package geometryThis body mandates standard dimensions for types of packagesCompanies provide set of technical specificationsMaterial of construction, dimensional features, electrical, thermal and reliability performance
14 Logic and Memory Packages Total number of package pin outs to the PWB depends upon data being processedTotal pin counts vary from few dozen to over a thousandMemory chips – few I/O pinsLogic chips – higher number of gates/circuits – more pinsWide bandwidth networking switches for transmission over the internet – over 1000 I/O pinsPackage pins distributed between:SignalPowerCommon reference voltage or groundSystem performance ↑ - total pin count ↑High performance - ↑ power and ground pins in order to reduce electrical noise during fast circuit switching.
15 7.4 Fundamentals of SCP 7.1 Single chip package (SCP) 7.2 Functions of a SCPs7.3 Types of SCPs7.4 Fundamentals of SCP7.5 Materials, Processes, Properties7.6 Characteristics of SCPs7.7 Summary and Future trends
16 7.4 Fundamentals of SCP The need for I/O determined be Rent’s Rule Designers use it in estimating the number of required package pins or I/O terminals (N), given the total number of gates (M)K is constant – the average number of terminals required by one logic circuitp is constant – depends on system typeFour main classes of application:1. memory (static and dynamic RAMs)2. microprocessors3. gate arrays (FPGAs)4. high-performance custom logic chips (“supercomputers”)
17 Relationship between chip I/Os and the number of chip circuits for various applications
18 I/O Pitch and Distribution I/O pitch definedPeripheral vs. Area (BGA)20mm package at 0.2mm pitch – 10,000 I/Os
19 What package to use – board assembly yield The first pass manufacturing yield at IC assembly for various packages are:The most important reasons for these yields:Contribution of the pitchSelf-alignment of solders to minimize shorts between two neighboring connectionsCoplanarity of leads parallel to the boardSolder wettingSolder ball collapse
20 Materials Influence Performance Electrical PerformanceRC delay – influence the speed of signal propagation through the packageV = C / square root of dielectric constantV is signal propagationC is speed of light
21 Thermal PerformanceThermal dissipation capabilities dependent on the materials with which SCP are made.Intel’s microprocessor ICs – 4W in 198930W currently100W in near future
22 Single Chip Packages Peripheral: DIP to PLCC to QFP to fine pitch QFP DIP, SOP, and QFPArea Array: Ceramic and plastic PGA to BGA to fine pitch BGAFlip Chip: Ceramic flip chip to organic flip chip
23 DIP: Dual In line Package Invented by Bryan Rogers in the early 1960s with 14 leadsAdopted by Texas Instruments in 1962Plastic or Ceramic versionEarliest industry standardLow pin counts – 8 to 48 pin rangeMemory and logic microcontrollersInterconnect to the next level provided by copperLead pitches of 1.75mm and 2.5mmNot preferred when space is a critical design constraint
24 SOP: Small Outline Package Well-suited for 24 to 48 pin memory packagingCell phones, pagers, PCMCIA cardsSimilar to DIP by using copper leadframe for pinsLeads have minimum standoff – making it easier to use in a surface mount assembly process to attach to the circuit board.
25 QFP: Quad Flat PackPlastic QFP – established member of the family of peripherally-leaded packagesMain difference – runs around all four sidesEnables higher pin count – up to 304 pinsThe most common usage – 48 to 128 rangeVery popular choice for lower cost microprocessors and other ICs for portable systemsCeramic QFP preferred when resistance to high temperatures and humidity becomes an important design parameter.
26 Area Array Packages The first high volume PGA package in 1982 1993, Motorola started shipping BGASince, packages have been “hot spot”SOP and QFP more expensiveLast few years – With finer pitch and lower cost, Chip Scale Package (CSP) count as low as 36 or less.CSP twice as expensive as small outline packages.High I/O for BGA, small size for CSPDistinguish between CSP and BGA:A Ball-Grid-Array is an array package with a ball pitch of 0.8mm or greater. Includes very high leadcount packages (>500 I/O)A Chip-Scale-Package is an array package with a ball pitch of 0.8mm or less (0.5, 0.75, or 0.8) and area no more than 50% more than the IC.
27 BGA: Ball Grid Array Advantages: Overcomes many size and performance limitations of peripherally-leaded packagesGreater number of I/Os at larger pitch preventing solder shorts.Basic types:Plastic (PBGA)Ceramic (CBGA)Tape (TBGA)Advantages:SizePerformanceEase of assembly
28 CSP: Chip Scale Package Size advantage. Only 50% larger area than the silicon wafer and only 20% larger circumference.This makes it one of the most important package types.
29 Materials, Processes, and Properties Typical elements of an SCP:Base substrate for wiringInterconnects between chip and packageInterconnect scheme between package and PCBEncapsulation to mechanically and chemically protect the chip and for thermal managementAdhesive materials to attach chip to substrate (underfill)Materials chosen must be:Physically strongCorrosion resistantWithstand temperature and environmental conditions
30 Materials Common Package Materials: Plastic molding compounds (QFPs) Organic laminates such as FR-4, BT-epoxy (BGAs)Ceramics, both high (HTCC) and low temperature (LTCC) used in PGAs and BGAsThin film flex and tape matreialsBy volume the majority of SCPs are laminatesManufacturability in large arrays makes them cheapAbility to use copper conductors can give better electrical performanceHigh-frequency and high pin count use ceramicsMost common is alumina or HTCCSuperior strength, moisture, and temperature toleranceHigh processing temperature requires molybdenum or tungsten conductors
31 Encapsulants, Lids, and Adhesives Package type and application specific:Copper lids or slugs in contact with the silicon can provide an improved thermal interfaceLow cost molding compounds or “globtops” can be used to seal and protect devicesVariety of adhesives are used to attach the device to the package:Silver filled epoxyGold/gold-silicon compounds
32 Electrical Characteristics Basic parameters of a package are:Line resistanceLoading capacitanceInductanceModels used to evaluate SCPs must account for all elements of a packageA good package exhibits minimum switching noise at the frequencies of operation
33 Packaging Efficiency Ratio of IC area to Package area Very critical in portable electronics
34 Reliability A major issue with Medical devicesHigh up-time devicesAutomotive and airborne componentsFull testing suite might take 4+ months to runAccelerated testing of expected loads:Thermal shockShipping shockVibrationHumidityChemical exposure
35 Cost Price premium for clock speed Relative cost of package to IC will determine what format is usedHigher cost BGAs and CSPs can be justified for decreased size
36 Future TrendsTrends driven by size, cost, reliability and increasing electrical performance.