Download presentation

Presentation is loading. Please wait.

Published byEzequiel Brimm Modified over 2 years ago

1
Unit 9 Multiplexers, Decoders, and Programmable Logic Devices Ku-Yaw Chang canseco@mail.dyu.edu.tw Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University

2
22004/03/17Fundamentals of Logic Design Contents 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders 9.5 Read-Only Memories 9.6 Programmable Logic Devices 9.7 Complex Programmable Logic Devices 9.8 Field Programmable Gate Arrays

3
32004/03/17Fundamentals of Logic Design Introduction Integrated Circuits (ICs) SSI : Small-scale integration SSI : Small-scale integration MSI : Medium-scale integration MSI : Medium-scale integration LSI : Large-scale integration LSI : Large-scale integration VLSI : Very-large-scale integration VLSI : Very-large-scale integration

4
42004/03/17Fundamentals of Logic Design Introduction SSI NAND, NOR, AND, OR, inverters, flip-flops NAND, NOR, AND, OR, inverters, flip-flops 1 to 4 gates, six inverters, 1 or 2 flip-flops 1 to 4 gates, six inverters, 1 or 2 flip-flopsMSI adders, multiplexers, decoders, register, counters adders, multiplexers, decoders, register, counters 12 to 100 gates 12 to 100 gatesLSI 100 to a few thousand gates 100 to a few thousand gates VLSI : Very-large-scale integration Several thousand gates or more Several thousand gates or more

5
52004/03/17Fundamentals of Logic Design IC classification According to how many transistors were integrated on one single chip: SSI (Small Scale Integration) : 64 SSI (Small Scale Integration) : 64 MSI (Medium Scale Integration): 1,024 MSI (Medium Scale Integration): 1,024 LSI (Large Scale Integration) : 65,000 LSI (Large Scale Integration) : 65,000 VLSI (Very Large Scale Integration) more than 65000 VLSI (Very Large Scale Integration) more than 65000 SVLSI (Super Very Large Scale Integration) : > 500,000 SVLSI (Super Very Large Scale Integration) : > 500,000

6
62004/03/17Fundamentals of Logic Design Introduction MultiplexersDecoders/Encoders Three-state buffers ROMsPLDsPLAsPALsCPLDsFPGAs

7
72004/03/17Fundamentals of Logic Design Contents 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders 9.5 Read-Only Memories 9.6 Programmable Logic Devices 9.7 Complex Programmable Logic Devices 9.8 Field Programmable Gate Arrays

8
82004/03/17Fundamentals of Logic Design Multiplexers Also called data selector Abbreviated as MUX Consist of A group of data inputs A group of data inputs A group of control inputs A group of control inputs To select one of the data inputs and connect it to the output terminal

9
92004/03/17Fundamentals of Logic Design 2-to-1 Multiplexers A = 0 Z = I 0 Z = I 0 Logic equation: Z = AI 0 + AI 1 A = 1 Z = I 1 Z = I 1

10
102004/03/17Fundamentals of Logic Design 4-to-1 Multiplexers Logic equation Z = ABI 0 + ABI 1 + ABI 2 + ABI 3 Z = ABI 0 + ABI 1 + ABI 2 + ABI 3

11
112004/03/17Fundamentals of Logic Design Multiplexers

12
122004/03/17Fundamentals of Logic Design Multiplexers A multiplexers with n control inputs To select any of 2 n data inputs To select any of 2 n data inputs General equation General equation Z = m k I k Z = m k I kwhere m k is a minterm of the n control variables m k is a minterm of the n control variablesand I k is the corresponding data input I k is the corresponding data input k = 0 2 n -1

13
132004/03/17Fundamentals of Logic Design Multiplexers Logic diagram for 8-to-1 MUX

14
142004/03/17Fundamentals of Logic Design Multiplexers Frequently used to select the data To be processed or stored To be processed or stored Quad Multiplexer to select data A = 0 : x 0 x 1 x 2 x 3 A = 0 : x 0 x 1 x 2 x 3 A = 1 : y 0 y 1 y 2 y 3 A = 1 : y 0 y 1 y 2 y 3

15
152004/03/17Fundamentals of Logic Design Bus A bus Several logic signals my be grouped together Several logic signals my be grouped together Represented by a single heavy line. Represented by a single heavy line. Number of bits in the bus A diagonal slash through a bus with a number beside it A diagonal slash through a bus with a number beside it A = 0 X appear on bus Z X appear on bus Z A = 1 Y appear on bus Z Y appear on bus Z

Similar presentations

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google