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Unit 7 Multi-Level Gate Circuits / NAND and NOR Gates Ku-Yaw Chang canseco@mail.dyu.edu.tw Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University

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22004/03/04Fundamentals of Logic Design Contents 7.1 Multi-Level Gate Circuits 7.2NAND and NOR Gates 7.3Design of Two-Level Circuits Using NAND and NOR Gates 7.4Design of Multi-Level NAND and NOR Gate Circuits 7.5Circuit Conversion Using Alternative Gate Symbols 7.6Design of Two-Level, Multiple-Output Circuits 7.7Multiple-Output NAND and NOR Circuits

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32004/03/04Fundamentals of Logic Design 7.4 Design of Multi-Level NAND- and NOR-Gates Circuits Multi-Level NAND-gate circuits Simplify the switching function to be realized. Simplify the switching function to be realized. Design a multi-level circuit of AND and OR gates. The output gate must be OR. AND-gate outputs cannot be used as AND-gate inputs; OR-gate outputs cannot be used as OR-gate inputs. Design a multi-level circuit of AND and OR gates. The output gate must be OR. AND-gate outputs cannot be used as AND-gate inputs; OR-gate outputs cannot be used as OR-gate inputs. Number the levels starting with the output gate as level 1. Replace all gates with NAND gates, leaving all interconnections between unchanged. Leave the inputs to levels 2, 4, 6, …unchanged. Invert any literals which appear as inputs to levels 1, 3, 5,… Number the levels starting with the output gate as level 1. Replace all gates with NAND gates, leaving all interconnections between unchanged. Leave the inputs to levels 2, 4, 6, …unchanged. Invert any literals which appear as inputs to levels 1, 3, 5,…

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42004/03/04Fundamentals of Logic Design Multi-Level NAND-gate circuits

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52004/03/04Fundamentals of Logic Design Contents 7.1 Multi-Level Gate Circuits 7.2NAND and NOR Gates 7.3Design of Two-Level Circuits Using NAND and NOR Gates 7.4Design of Multi-Level NAND and NOR Gate Circuits 7.5Circuit Conversion Using Alternative Gate Symbols 7.6Design of Two-Level, Multiple-Output Circuits 7.7Multiple-Output NAND and NOR Circuits

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62004/03/04Fundamentals of Logic Design 7.5Circuit Conversion Using Alternative Gate Symbols An inverter can be represented by Inversion bubble Inversion bubble At the input At the output

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72004/03/04Fundamentals of Logic Design Alternative Gate Symbols AND, OR, NAND, and NOR gates Based on DeMorgans law Based on DeMorgans law

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82004/03/04Fundamentals of Logic Design Alternative Gate Symbols Why alternative symbols? Facilitate the analysis and design of NAND and NOR gate circuits Facilitate the analysis and design of NAND and NOR gate circuits

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92004/03/04Fundamentals of Logic Design NAND Gate Circuit Conversion

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102004/03/04Fundamentals of Logic Design Conversion to NOR Gates

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112004/03/04Fundamentals of Logic Design Conversion of AND-OR Circuit to NAND Gates Convert all AND gates to NAND gates Adding an inversion bubble at the output Adding an inversion bubble at the output Convert all OR gates to NAND gates Adding inversion bubbles at the inputs Adding inversion bubbles at the inputs An inverted output drives an inverted input No further action No further action

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122004/03/04Fundamentals of Logic Design Conversion of AND-OR Circuit to NAND Gates A non-inverted gate output drives an inverted gate input or vice versa Insert an inverter Insert an inverter A variable drives an inverted input Complement the variable Complement the variable

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132004/03/04Fundamentals of Logic Design Conversion of AND-OR Circuit to NAND Gates

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142004/03/04Fundamentals of Logic Design Contents 7.1 Multi-Level Gate Circuits 7.2NAND and NOR Gates 7.3Design of Two-Level Circuits Using NAND and NOR Gates 7.4Design of Multi-Level NAND and NOR Gate Circuits 7.5Circuit Conversion Using Alternative Gate Symbols 7.6Design of Two-Level, Multiple-Output Circuits 7.7Multiple-Output NAND and NOR Circuits

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152004/03/04Fundamentals of Logic Design 7.6 Design of Two-Level, Multiple-Output Circuits The realization of several functions of the same variables A more economical realization A more economical realization

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162004/03/04Fundamentals of Logic Design Multi-Output Function Given Functions F 1 (A, B, C, D) = m(11, 12, 13, 14, 15) F 1 (A, B, C, D) = m(11, 12, 13, 14, 15) F 2 (A, B, C, D) = m(3, 7, 11, 12, 13, 15) F 2 (A, B, C, D) = m(3, 7, 11, 12, 13, 15) F 3 (A, B, C, D) = m(3, 7, 12, 13, 14, 15) F 3 (A, B, C, D) = m(3, 7, 12, 13, 14, 15)

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172004/03/04Fundamentals of Logic Design Separate Realizations

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182004/03/04Fundamentals of Logic Design Multiple-Output Simplification F 1 = AB + ACD F 2 = ABC + CD F 3 = ACD + AB F 3 = ACD + AB AB: F 1 and F 3 CD (F 2 ) can be replaced by ACD + ACD F 2 = ABC + ACD + ACD F 2 = ABC + ACD + ACD

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192004/03/04Fundamentals of Logic Design Multiple-Output Realization

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202004/03/04Fundamentals of Logic Design Comparison Gates Gate Inputs Level Separate Realization 9212 Multiple-OutputRealization7182

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212004/03/04Fundamentals of Logic Design Multiple-Output Simplification If several solutions are available Try to minimize the total number of gates required Try to minimize the total number of gates required Choose the one with minimum gates inputs Choose the one with minimum gates inputs

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222004/03/04Fundamentals of Logic Design Contents 7.1 Multi-Level Gate Circuits 7.2NAND and NOR Gates 7.3Design of Two-Level Circuits Using NAND and NOR Gates 7.4Design of Multi-Level NAND and NOR Gate Circuits 7.5Circuit Conversion Using Alternative Gate Symbols 7.6Design of Two-Level, Multiple-Output Circuits 7.7Multiple-Output NAND and NOR Circuits

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232004/03/04Fundamentals of Logic Design 7.7Multiple-Output NAND and NOR Circuits

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242004/03/04Fundamentals of Logic Design Homework #1 1.7.1 2.7.3 3.7.4 4.7.8 5.7.10 6.7.17 7.7.19 8.7.20 9.7.25 10.7.26 Paper Submission, due on March 22, 2004. Late submission will not be accepted.

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