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Unit 11 Latches and Flip-Flops Ku-Yaw Chang Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh.

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Presentation on theme: "Unit 11 Latches and Flip-Flops Ku-Yaw Chang Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh."— Presentation transcript:

1 Unit 11 Latches and Flip-Flops Ku-Yaw Chang Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University

2 22004/04/26Latches and Flip-flops Outline 11.1Introduction 11.2Set-Reset Latch 11.3Gated D Latch 11.4Edge-Triggered D Flip-Flop 11.5S-R Flip-Flop 11.6J-K Flip-Flop 11.7T Flip-Flop 11.8Flip-Flops with Additional Inputs 11.9Summary

3 32004/04/26Latches and Flip-flops Gated D Latch Two inputs A data input (D) A data input (D) A gate input (G) A gate input (G) Constructed from an S-R latch and gates

4 42004/04/26Latches and Flip-flops Timing Diagram G = 1 The Q output follows the D input. The Q output follows the D input. Transparent latch Transparent latch G = 0 The Q output holds the last value of D (no state change) The Q output holds the last value of D (no state change)

5 52004/04/26Latches and Flip-flops Symbol and Truth Table GDQ Q+Q+Q+Q

6 62004/04/26Latches and Flip-flops Outline 11.1Introduction 11.2Set-Reset Latch 11.3Gated D Latch 11.4Edge-Triggered D Flip-Flop 11.5S-R Flip-Flop 11.6J-K Flip-Flop 11.7T Flip-Flop 11.8Flip-Flops with Additional Inputs 11.9Summary

7 72004/04/26Latches and Flip-flops D Flip-Flop Two inputs D (data) D (data) The output changes only in response to the clock, not to a change in D. Ck (clock) Ck (clock)

8 82004/04/26Latches and Flip-flops D Flip-Flop The output can change in response to a 0 to 1 transition on the clock input Triggered on the rising edge (or positive edge) Triggered on the rising edge (or positive edge) The output can change in response to a 1 to 0 transition on the clock input Triggered on the falling edge (or negative edge) Triggered on the falling edge (or negative edge) Active edge The clock edge (rising or falling) that triggers the flip-flop The clock edge (rising or falling) that triggers the flip-flop

9 92004/04/26Latches and Flip-flops D Flip-Flop The state after the active clock edge (Q + ) is equal to the input (D) before the active edge. Characteristic equation : Q + = D Characteristic equation : Q + = D DQ Q+Q+Q+Q

10 102004/04/26Latches and Flip-flops D Flip-Flop The output change are delayed Falling edge trigger Falling edge trigger

11 112004/04/26Latches and Flip-flops D Flip-Flop A rising-edge-triggered D flip-flop two gated D latches two gated D latches an inverter an inverter

12 122004/04/26Latches and Flip-flops D Flip-Flop Time Analysis

13 132004/04/26Latches and Flip-flops Setup and Hold Times Propagation delay is the time between the active edge of the clock the active edge of the clock the resulting change in the output the resulting change in the output If D changes at the same time as the active edge, the behavior is unpredictable. Setup time (t su ) the amount of time that D must be stable before the active edge the amount of time that D must be stable before the active edge Hold time (t h ) the amount of time that D must hold the same value after the active edge the amount of time that D must hold the same value after the active edge

14 142004/04/26Latches and Flip-flops Setup and Hold Times The times at which D is allowed to change are shaded in the following timing diagram.

15 152004/04/26Latches and Flip-flops Determination of Minimum Clock Period


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