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Unit 13 Analysis of Clocked Sequential Circuits Ku-Yaw Chang Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University

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22004/05/24Analysis of Clocked Sequential Circuits Outline 13.1A Sequential Parity Checker 13.2Analysis by Signal Tracing and Timing Charts 13.3 State Tables and Graphs 13.4 General Models for Sequential Circuits

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32004/05/24Analysis of Clocked Sequential Circuits State Tables

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42004/05/24Analysis of Clocked Sequential Circuits State Graph

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52004/05/24Analysis of Clocked Sequential Circuits Construct the State Table 1.Determine the flip-flop input equations and the output equations from the circuit. 2.Derive the next-state equation for each flip-flop from its input equations, using one of the following relations: D flip-flop Q + = D T flip-flop Q + = T Q : 3.Plot a next-state map for each flip-flop. 4.Combine these maps to form the state table. A transition table A transition table

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62004/05/24Analysis of Clocked Sequential Circuits First Example

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72004/05/24Analysis of Clocked Sequential Circuits Construct the State Table 1.Determine the flip-flop input equations and the output equations from the circuit. 2.Derive the next-state equation for each flip-flop from its input equations, using one of the following relations: D flip-flop Q + = D T flip-flop Q + = T Q : 3.Plot a next-state map for each flip-flop. 4.Combine these maps to form the state table. A transition table A transition table

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82004/05/24Analysis of Clocked Sequential Circuits Construct the State Table Determine the flip-flop input equations and the output equations from the circuit. D A = X B D A = X B D B = X + A D B = X + A Z = A B Z = A B

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92004/05/24Analysis of Clocked Sequential Circuits Construct the State Table 1.Determine the flip-flop input equations and the output equations from the circuit. 2.Derive the next-state equation for each flip-flop from its input equations, using one of the following relations: D flip-flop Q + = D T flip-flop Q + = T Q : 3.Plot a next-state map for each flip-flop. 4.Combine these maps to form the state table. A transition table A transition table

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102004/05/24Analysis of Clocked Sequential Circuits Construct the State Table 2.Derive the next-state equation for each flip-flop from its input equations, using one of the following relations: D flip-flop Q + = D D-CE flip-flop Q + = D · CE + Q · CE T flip-flop Q + = T Q S-R flip-flop Q + = S + RQ J-K flip-flop Q + = JQ + KQ A + = X B A + = X B B + = X + A B + = X + A

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112004/05/24Analysis of Clocked Sequential Circuits Construct the State Table 1.Determine the flip-flop input equations and the output equations from the circuit. 2.Derive the next-state equation for each flip-flop from its input equations, using one of the following relations: D flip-flop Q + = D T flip-flop Q + = T Q : 3.Plot a next-state map for each flip-flop. 4.Combine these maps to form the state table. A transition table A transition table

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122004/05/24Analysis of Clocked Sequential Circuits Construct the State Table 3.Plot a next-state map for each flip-flop. A + = X B B + = X + A

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132004/05/24Analysis of Clocked Sequential Circuits Construct the State Table 1.Determine the flip-flop input equations and the output equations from the circuit. 2.Derive the next-state equation for each flip-flop from its input equations, using one of the following relations: D flip-flop Q + = D T flip-flop Q + = T Q : 3.Plot a next-state map for each flip-flop. 4.Combine these maps to form the state table. A transition table A transition table

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142004/05/24Analysis of Clocked Sequential Circuits Construct the State Table 4.Combine these maps to form the state table. A transition table A transition table

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152004/05/24Analysis of Clocked Sequential Circuits Moore State Graph

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162004/05/24Analysis of Clocked Sequential Circuits Second Example

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172004/05/24Analysis of Clocked Sequential Circuits Construct the State Table Determine the flip-flop input equations and the output equations from the circuit. J A = XB, K A = X J A = XB, K A = X J B = X, K B = XA J B = X, K B = XA Z = XB+XA+XAB Z = XB+XA+XAB

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182004/05/24Analysis of Clocked Sequential Circuits Construct the State Table 2.Derive the next-state equation for each flip-flop from its input equations, using one of the following relations: D flip-flop Q + = D D-CE flip-flop Q + = D · CE + Q · CE T flip-flop Q + = T Q S-R flip-flop Q + = S + RQ J-K flip-flop Q + = JQ + KQ A + = J A A + K A A = XBA + XA A + = J A A + K A A = XBA + XA B + = J B B + K B B = XB + (AX)B = XB+ XB + AB B + = J B B + K B B = XB + (AX)B = XB+ XB + AB Z = XAB + XB + XA Z = XAB + XB + XA

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192004/05/24Analysis of Clocked Sequential Circuits Construct the State Table 3.Plot a next-state and output map.

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202004/05/24Analysis of Clocked Sequential Circuits Construct the State Table 4.Combine these maps to form the state table.

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212004/05/24Analysis of Clocked Sequential Circuits Mealy State Graph

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222004/05/24Analysis of Clocked Sequential Circuits Third Example Serial Adder xixixixi yiyiyiyi cicicici c i+1 sisisisi

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232004/05/24Analysis of Clocked Sequential Circuits Timing Diagram

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242004/05/24Analysis of Clocked Sequential Circuits Serial Adder Initially the carry flip-flop must be cleared C 0 =0 C 0 =0 Start by adding the least-significant (rightmost) bits in each word. Reading the sum output just before the rising edge of the clock

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252004/05/24Analysis of Clocked Sequential Circuits State Graph A Mealy machine Inputs: x i and y i Inputs: x i and y i Output: s i Output: s i Two states represent a carry (c i ) S 0 for 0 and S 1 for 1

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262004/05/24Analysis of Clocked Sequential Circuits Multiple Inputs and Outputs

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272004/05/24Analysis of Clocked Sequential Circuits Multiple Inputs and Outputs

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