# Unit 13 Analysis of Clocked Sequential Circuits

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Unit 13 Analysis of Clocked Sequential Circuits
Ku-Yaw Chang Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University

Analysis of Clocked Sequential Circuits
Outline 13.1 A Sequential Parity Checker 13.2 Analysis by Signal Tracing and Timing Charts 13.3 State Tables and Graphs 13.4 General Models for Sequential Circuits 2004/05/24 Analysis of Clocked Sequential Circuits

Analysis of Clocked Sequential Circuits
State Tables 2004/05/24 Analysis of Clocked Sequential Circuits

Analysis of Clocked Sequential Circuits
State Graph 2004/05/24 Analysis of Clocked Sequential Circuits

Construct the State Table
Determine the flip-flop input equations and the output equations from the circuit. Derive the next-state equation for each flip-flop from its input equations, using one of the following relations: D flip-flop Q+ = D T flip-flop Q+ = T  Q : Plot a next-state map for each flip-flop. Combine these maps to form the state table. A transition table 2004/05/24 Analysis of Clocked Sequential Circuits

Analysis of Clocked Sequential Circuits
First Example 2004/05/24 Analysis of Clocked Sequential Circuits

Construct the State Table
Determine the flip-flop input equations and the output equations from the circuit. Derive the next-state equation for each flip-flop from its input equations, using one of the following relations: D flip-flop Q+ = D T flip-flop Q+ = T  Q : Plot a next-state map for each flip-flop. Combine these maps to form the state table. A transition table 2004/05/24 Analysis of Clocked Sequential Circuits

Construct the State Table
Determine the flip-flop input equations and the output equations from the circuit. DA = X  B’ DB = X + A Z = A  B 2004/05/24 Analysis of Clocked Sequential Circuits

Construct the State Table
Determine the flip-flop input equations and the output equations from the circuit. Derive the next-state equation for each flip-flop from its input equations, using one of the following relations: D flip-flop Q+ = D T flip-flop Q+ = T  Q : Plot a next-state map for each flip-flop. Combine these maps to form the state table. A transition table 2004/05/24 Analysis of Clocked Sequential Circuits

Construct the State Table
Derive the next-state equation for each flip-flop from its input equations, using one of the following relations: D flip-flop Q+ = D D-CE flip-flop Q+ = D · CE + Q · CE’ T flip-flop Q+ = T  Q S-R flip-flop Q+ = S + R’Q J-K flip-flop Q+ = JQ’ + K’Q A+ = X  B’ B+ = X + A 2004/05/24 Analysis of Clocked Sequential Circuits

Construct the State Table
Determine the flip-flop input equations and the output equations from the circuit. Derive the next-state equation for each flip-flop from its input equations, using one of the following relations: D flip-flop Q+ = D T flip-flop Q+ = T  Q : Plot a next-state map for each flip-flop. Combine these maps to form the state table. A transition table 2004/05/24 Analysis of Clocked Sequential Circuits

Construct the State Table
Plot a next-state map for each flip-flop. A+ = X  B’ B+ = X + A 2004/05/24 Analysis of Clocked Sequential Circuits

Construct the State Table
Determine the flip-flop input equations and the output equations from the circuit. Derive the next-state equation for each flip-flop from its input equations, using one of the following relations: D flip-flop Q+ = D T flip-flop Q+ = T  Q : Plot a next-state map for each flip-flop. Combine these maps to form the state table. A transition table 2004/05/24 Analysis of Clocked Sequential Circuits

Construct the State Table
Combine these maps to form the state table. A transition table 2004/05/24 Analysis of Clocked Sequential Circuits

Analysis of Clocked Sequential Circuits
Moore State Graph 2004/05/24 Analysis of Clocked Sequential Circuits

Analysis of Clocked Sequential Circuits
Second Example 2004/05/24 Analysis of Clocked Sequential Circuits

Construct the State Table
Determine the flip-flop input equations and the output equations from the circuit. JA = XB, KA = X JB = X, KB = XA Z = XB’+XA+X’A’B 2004/05/24 Analysis of Clocked Sequential Circuits

Construct the State Table
Derive the next-state equation for each flip-flop from its input equations, using one of the following relations: D flip-flop Q+ = D D-CE flip-flop Q+ = D · CE + Q · CE’ T flip-flop Q+ = T  Q S-R flip-flop Q+ = S + R’Q J-K flip-flop Q+ = JQ’ + K’Q A+ = JAA’ + KA’A = XBA’ + X’A B+ = JBB’ + KB’B = XB’ + (AX)’B = XB’+ X’B + A’B Z = X’A’B + XB’ + XA 2004/05/24 Analysis of Clocked Sequential Circuits

Construct the State Table
Plot a next-state and output map. 2004/05/24 Analysis of Clocked Sequential Circuits

Construct the State Table
Combine these maps to form the state table. 2004/05/24 Analysis of Clocked Sequential Circuits

Analysis of Clocked Sequential Circuits
Mealy State Graph 2004/05/24 Analysis of Clocked Sequential Circuits

Analysis of Clocked Sequential Circuits
Third Example Serial Adder xi yi ci ci+1 si 1 2004/05/24 Analysis of Clocked Sequential Circuits

Analysis of Clocked Sequential Circuits
Timing Diagram 2004/05/24 Analysis of Clocked Sequential Circuits

Analysis of Clocked Sequential Circuits
Serial Adder Initially the carry flip-flop must be cleared C0=0 Start by adding the least-significant (rightmost) bits in each word. Reading the sum output just before the rising edge of the clock 2004/05/24 Analysis of Clocked Sequential Circuits

Analysis of Clocked Sequential Circuits
State Graph A Mealy machine Inputs: xi and yi Output: si Two states represent a carry (ci) S0 for 0 and S1 for 1 2004/05/24 Analysis of Clocked Sequential Circuits

Multiple Inputs and Outputs
2004/05/24 Analysis of Clocked Sequential Circuits

Multiple Inputs and Outputs
2004/05/24 Analysis of Clocked Sequential Circuits