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Unit 9 Multiplexers, Decoders, and Programmable Logic Devices Ku-Yaw Chang Assistant Professor, Department of Computer Science.

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Presentation on theme: "Unit 9 Multiplexers, Decoders, and Programmable Logic Devices Ku-Yaw Chang Assistant Professor, Department of Computer Science."— Presentation transcript:

1 Unit 9 Multiplexers, Decoders, and Programmable Logic Devices Ku-Yaw Chang Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University

2 22004/03/29Fundamentals of Logic Design Contents 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders 9.5 Read-Only Memories 9.6 Programmable Logic Devices 9.7 Complex Programmable Logic Devices 9.8 Field Programmable Gate Arrays

3 32004/03/29Fundamentals of Logic Design Buffer A gate output Be connected to a limited number of other device inputs without degrading the performance Be connected to a limited number of other device inputs without degrading the performance A simple buffer Increase the driving capability of a gate input Increase the driving capability of a gate input

4 42004/03/29Fundamentals of Logic Design Add Buffer No bubble F = C F = C

5 52004/03/29Fundamentals of Logic Design Three-State Buffers A logic gate will not operate correctly if the outputs of two or more gates or other logic devices are directly connected to each other. In some cases, damage to the gates may result. In some cases, damage to the gates may result.

6 62004/03/29Fundamentals of Logic Design Three-State Buffers Also called tri-state buffers B = 1 The output C equals A The output C equals A B = 0 The output C acts like an open circuit The output C acts like an open circuit A Hi-Z (high-impedance) A Hi-Z (high-impedance)

7 72004/03/29Fundamentals of Logic Design Four Types The symbol Z represents the high-impedance state.

8 82004/03/29Fundamentals of Logic Design Data Selection The outputs of two three-state buffers are tied together. B = 0 B = 0 D = A B = 1 B = 1 D = C D = BA + BC D = BA + BC Logically equivalent to using a 2-to-1 multiplexer

9 92004/03/29Fundamentals of Logic Design Two Three-State Buffers Connect two three-state buffer outputs together

10 102004/03/29Fundamentals of Logic Design Four Sources

11 112004/03/29Fundamentals of Logic Design Bi-Directional Input/Output Pin

12 122004/03/29Fundamentals of Logic Design Contents 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders 9.5 Read-Only Memories 9.6 Programmable Logic Devices 9.7 Complex Programmable Logic Devices 9.8 Field Programmable Gate Arrays

13 132004/03/29Fundamentals of Logic Design 3-to-8 Line Decoder Exactly one of the output lines will be 1 for each combination of the values of the input variables.

14 142004/03/29Fundamentals of Logic Design 4-to-10 Line Decoder

15 152004/03/29Fundamentals of Logic Design 4-to-10 Line Decoder

16 162004/03/29Fundamentals of Logic Design Decoder In general, an n-to-2 n line decoder generate all 2 n minterms (or maxterms) of the n input variables. The outputs are defined as follows: y i =m i, i =0 to 2 n -1 (noninverted outputs) y i =m i, i =0 to 2 n -1 (noninverted outputs) y i =m i = M i, i=0 to 2 n -1 (inverted outputs) y i =m i = M i, i=0 to 2 n -1 (inverted outputs)

17 172004/03/29Fundamentals of Logic Design Decoder n-variable functions be realized by ORing together selected minterm outputs from a decoder be realized by ORing together selected minterm outputs from a decoder outputs are inverted outputs are inverted Use NAND gates

18 182004/03/29Fundamentals of Logic Design Realization of a Multiple-Output Circuit Using a Decoder f 1 (a,b,c,d) = m 1 + m 2 + m 4 f 1 = (m 1 m 2 m 4 ) f 1 = (m 1 m 2 m 4 ) f 2 (a,b,c,d) = m 4 + m 7 + m 9 f 2 = (m 4 m 7 m 9 ) f 2 = (m 4 m 7 m 9 )

19 192004/03/29Fundamentals of Logic Design Realization of a Multiple-Output Circuit Using a Decoder

20 202004/03/29Fundamentals of Logic Design Encoder Perform the inverse function of a decoder

21 212004/03/29Fundamentals of Logic Design 8-to-3 Priority Encoder

22 222004/03/29Fundamentals of Logic Design Contents 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders 9.5 Read-Only Memories 9.6 Programmable Logic Devices 9.7 Complex Programmable Logic Devices 9.8 Field Programmable Gate Arrays

23 232004/03/29Fundamentals of Logic Design ROM Read-Only Memories An array of semiconductor devices that are interconnected to store an array of binary data An array of semiconductor devices that are interconnected to store an array of binary data Can be read out whenever desired Can be read out whenever desired Cannot be changed under normal operation conditions Cannot be changed under normal operation conditions

24 242004/03/29Fundamentals of Logic Design ROM WordAddress ABC = 010 F 0 F 1 F 2 F 3 = 0111 F 0 F 1 F 2 F 3 = 0111

25 252004/03/29Fundamentals of Logic Design ROM n input lines and m output lines 2 n words 2 n words Each word is m bits long Each word is m bits long

26 262004/03/29Fundamentals of Logic Design ROM A 2 n * m ROM can realize m functions of n variables Sizes for commercial available ROMs range From 32 words * 4 bits From 32 words * 4 bits To 512K words * 8 bits or larger To 512K words * 8 bits or larger

27 272004/03/29Fundamentals of Logic Design ROM Consist of A decoder A decoder A memory array A memory array

28 282004/03/29Fundamentals of Logic Design Internal Structure

29 292004/03/29Fundamentals of Logic Design Internal Structure F 0 = m(0, 1, 4, 6) = AB+AC F 1 = m(2, 3, 4, 6, 7) = B+AC F 2 = m(0, 1, 2, 6) = AB+BC F 3 = m(2, 3, 5, 6, 7) = AC+B

30 302004/03/29Fundamentals of Logic Design Hexadecimal to ASCII Code Converter Multiple-output combinational circuits can easily be realized using ROMs.

31 312004/03/29Fundamentals of Logic Design Hexadecimal to ASCII Code Converter

32 322004/03/29Fundamentals of Logic Design ROM Realization of Code Converter

33 332004/03/29Fundamentals of Logic Design ROM Types Mask-programmable ROMs Require a special mask Require a special mask Programmed during the manufacturing process Programmed during the manufacturing process Economically feasible only if a large quantity Economically feasible only if a large quantity Programmable ROMs (PROMs) Be written only once Be written only once PROM programmer or PROM burner Be manufactured as blank memory Be manufactured as blank memory

34 342004/03/29Fundamentals of Logic Design ROM Types Erasable Programmable ROMs (EPROMs) Retain contents until being exposed to ultraviolet light Retain contents until being exposed to ultraviolet light Reprogram the memory Reprogram the memory Electrically Erasable Programmable ROMs (EEPROMs) Be erased by exposing it to an electrical charge Be erased by exposing it to an electrical charge Reprogram the memory Reprogram the memory

35 352004/03/29Fundamentals of Logic Design ROM Types Flash memory (Flash EEPROMs) Be erased and reprogrammed in blocks instead of one byte at a time Be erased and reprogrammed in blocks instead of one byte at a time

36 362004/03/29Fundamentals of Logic Design Flash Memory Many modern PCs have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Such a BIOS is sometimes called a flash BIOS.

37 372004/03/29Fundamentals of Logic Design Flash Memory Compact Flash (CF) Card Digital cameras, music players… Digital cameras, music players… Type I CF cards: 3.3 mm thick Type I CF cards: 3.3 mm thick Type II CF cards: 5.5 mm thick Type II CF cards: 5.5 mm thick Secure Digital (SD) Card MultiMedia Card (MMC)


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