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(Pucknell p:-134-178) (Neil west - p:-317-357)

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Switch logic Gate logics Combinational logic Clocked sequential circuits Clocking Strategies,PLL

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Introduction Large systems are composed of sub-systems, known as Leaf-Cells The most basic leaf cell is the common logic gate (inverter, nand,..etc) Structured Design High regularity Leaf cells replicated many times and interconnected to form the system Logical and systematic approach to VLSI design is essential

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Architectural issues In all design process, a logical and systematic approach is essential Define the requirements Partition the overall architecture into appropriate subsystems Consider communication paths carefully Floor plan :how the system is to map onto the silicon Aim for regular structures Draw stick or symbolic diagrams Convert each cell to a layout Carry out a design rule check on each cell Simulate the performance of each subsystem

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Switch Logic Switch logic is based on the pass transistor or on transmission gates. 1. Pass transistor 2. Gate(restoring) logic

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Pass transistor

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Pass transistor and transmission-gate switches and switch logic may be formed from simple n- p-pass transistors or from transmission-gate Signal degradation occurs in Pass transistor logic No Signal degradation occurs in transmission gate,but more area is occupied S S Vin Vout S

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Gate(restoring) logic Gate logic is based on the general arrangement circuits Ex : Inverter, Nand Nor, And, Or….

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Inverter Some of the commonly used inverter circuit diagrams V out V dd = 5V V in V out V dd = 5V V in

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nMOS inverter 16λ 2λ2λ 2λ2λ 8λ8λ 4λ4λ 2λ2λ

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Two input nMOS,CMOS, Nand Gate

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1) nMOS Nand gate area requirement: As inputs are added, so must there be a corresponding adjustment of the length of the pull-up transistor channel to maintain the required overall ratio 2) nMOS Nand gate delay: For n inputs, then the length and resistance of the pull-up transistor must be increased by factor of n to keep correct ratio. Delay associated with the nMOS Nand gate Г Nand =nГ Nand gate two significant factors

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Two input nMOS,CMOS Nor gate

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Since both transistor of the nMOS Nor gate provide a path to ground from the pull-up transistor, the ratios must be such that any one conducting pull-down transistor will give the appropriate inverter-like transfer characteristic.

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Pseudo-nMOS logic The circuit is replaced by depletion mode pull-up transistor of the standard nMOS circuits with a p- transistor with gate connected to Vss. Ex: 3 input NAND gate..

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Dynamic CMOS logic Charge sharing problem unless the inputs are constrained not to change during the on period of the clock Single phase dynamic logic structures cannot be cascaded

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Clocked CMOS logic Logic is implemented in both n- and p-transistors in the form of a p-block and n-block structure The logic is evaluated only during on period of the clock

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n-p CMOS logic The actual logic blocks are alternately n and p in a cascaded structure Logic operation depends on clock φ and clock bar φ alternatively

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Examples of structured design (Combinational logic) A parity generator Bus arbitration logic for n-line bus Multiplexers (Data selectors) A general logic function block A four-line gray code to binary code converter The programmable logic array (PLA)

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Parity generator A i =1 parity is changed, P i =P i-1 A i =0 parity is unchanged, P i =P i-1 P=1 even number of 1s at input P=0 odd number of 1s at input A0 A1 A2 An-1 An P P

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Stick diagram Pi P i-1 Ai

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Bus arbitration logic for n-line bus If the highest priority line An is Hi (logic 1), then output line A p n will be Hi and all other output line Lo (logic o), irrespective of the state of the other input lines A1----An-1. Similarly, A p n-1 will be Hi and all other output line Lo (logic o), irrespective -1 will be Hi only when An-1 is Hi and An is Lo; again the state of all input lines of lower priority (A1----An-2)will have no effect and all other output lines will be Lo.

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n-line bus Stick diagram An An-1 An-2 0 0 0 ApnApn A p n-1 A p n-2 An An-1

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Multiplexers (Data selectors) MUX I0 I1 I2 I3 S1 S1 S0 S0 Z

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MUX Stick diagram I0 I1 I2 I3 S1 S1 S0 S0 Z

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A general logic function block AABBAABB C3 C2 C1 C0 Z Data inputs Select inputs Nor, Nand 0 0 0 1 0 1 1 1

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A four-line gray code to binary code converter A0=G0 A1 A1=G1 A2 A2=G2 A3 A3=G3 } Exclusive-or operations

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The programmable logic array (PLA)

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o Lose sight of overall system requirements and restrictions o Use of buses to interconnect subsystems and circuits must always be most carefully considered. Bipolar drivers for Bus Lines Basic arrangements for Bus Lines Power dissipation for CMOS and BiCMOS circuits Current limitations Further aspects of Vdd and Vss rail distribution

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Bipolar drivers for Bus Lines Bus structures carrying data and control signals are generally long and connected to and trough a significant number of circuits and subsystems Propagation of signals may be a slow process The capacitive load driving properties of bipolar transistors in a BiCMOS process make bipolar drivers an attractive proposition for bus lines

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There are three classes of bus- passive,active and precharged A passive bus rail is a floating rail to which signals may be connected from drivers through series switches Basic arrangements for Bus Lines

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In active bus a common pull-up R p.u and n-type pull- down transistors or series n-type transistor logic

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The Precharged bus concept The precharged bus approach limits the effects of bus capacitance in that a single pull-up transister whch is turned on only during 2

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Power dissipation for CMOS and BiCMOS Circuits The overall dissipation is composed of two terms: 1) P1 the dissipation due to the leakage current I1 through an off transistor. Consequently, for n transistors, we have P1=n.I1.Vdd Where I1=0.1 nA, typically at room temperature. 2) Ps is the dissipation due to energy supplied to charge and discharge the capacitances associated with each switching circuit Ps=C L.V dd 2.f Total power dissipation Pt=P1+Ps Power dissipation for bipolar devices can be simply modeled by P=Vcc* Ic Ic is the current through the device

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Current limitations for Vdd and GND rails Metal migration for high current densities in metal conductors Aluminum conductor threshold value J th =1 to 2 mA

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Further aspects of Vdd and Vss rail distribution Limitations of distributive rails are: 1) Metal migration imposed current density restrictions 2) The IR drop due to rail series resistance 3) The series inductance of the rails

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IR drop and series inductance For a parent bus supplying current to other uniformly distributed short bus branches along the length L of the parent bus, then the current at any distance x from the source is given by I x =I L (1-x/L)

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series inductance The transmission line nature of any wiring introduces the possibility of voltage transients due to its self- inductance L0. the transient changes in voltage due to the presence of self-inductance can be modeled by V=L0 di/dt di/dt Is the rate of change of line current

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