3IntroductionLarge systems are composed of sub-systems, known as Leaf-CellsThe most basic leaf cell is the common logic gate (inverter, nand, ..etc)Structured DesignHigh regularityLeaf cells replicated many times and interconnected to form the systemLogical and systematic approach to VLSI design is essential
4Architectural issues Define the requirements In all design process, a logical and systematic approach is essentialDefine the requirementsPartition the overall architecture into appropriate subsystemsConsider communication paths carefullyFloor plan :how the system is to map onto the siliconAim for regular structuresDraw stick or symbolic diagramsConvert each cell to a layoutCarry out a design rule check on each cellSimulate the performance of each subsystem
5Switch LogicSwitch logic is based on the ‘pass transistor ‘ or on transmission gates.Pass transistorGate(restoring) logic
7Pass transistor and transmission-gate switches and switch logic may be formed from simple n- p-pass transistors or from transmission-gateSignal degradation occurs in Pass transistor logicNo Signal degradation occurs in transmission gate ,but more area is occupiedSS’VoutVinS
8Gate(restoring) logic Gate logic is based on the general arrangement circuitsEx : Inverter, Nand Nor, And, Or….
9Inverter Some of the commonly used inverter circuit diagrams Vdd = 5V VoutVdd = 5VVinVoutVdd = 5VVin
12Nand gate two significant factors nMOS Nand gate area requirement:As inputs are added, so must there be a corresponding adjustment of the length of the pull-up transistor channel to maintain the required overall rationMOS Nand gate delay:For n inputs, then the length and resistance of the pull-up transistor must be increased by factor of n to keep correct ratio.Delay associated with the nMOS Nand gateГNand =nГ
14Since both transistor of the nMOS Nor gate provide a path to ground from the pull-up transistor, the ratios must be such that any one conducting pull-down transistor will give the appropriate inverter-like transfer characteristic.
15Pseudo-nMOS logicThe circuit is replaced by depletion mode pull-up transistor of the standard nMOS circuits with a p-transistor with gate connected to Vss.Ex: 3 input NAND gate..
16Dynamic CMOS logicCharge sharing problem unless the inputs are constrained not to change during the on period of the clockSingle phase dynamic logic structures cannot be cascaded
17Clocked CMOS logicLogic is implemented in both n- and p-transistors in the form of a p-block and n-block structureThe logic is evaluated only during on period of the clock
18n-p CMOS logicThe actual logic blocks are alternately ‘n’ and ‘p’ in a cascaded structureLogic operation depends on clock φ and clock bar φ’ alternatively
19Examples of structured design (Combinational logic) A parity generatorBus arbitration logic for n-line busMultiplexers (Data selectors)A general logic function blockA four-line gray code to binary code converterThe programmable logic array (PLA)
20Parity generator Ai=1 parity is changed, Pi=P’i-1 A0 A1 A An-1 AnP=1 even number of 1’s at inputP=0 odd number of 1’s at inputAi=1 parity is changed, Pi=P’i-1Ai=0 parity is unchanged, Pi=Pi-1
22Bus arbitration logic for n-line bus If the highest priority line An is Hi (logic 1), then output line Apn will be Hi and all other output line Lo (logic o), irrespective of the state of the other input lines A1----An-1.Similarly , Apn-1 will be Hi and all other output line Lo (logic o), irrespective -1 will be Hi only when An-1 is Hi and An is Lo; again the state of all input lines of lower priority (A1----An-2)will have no effect and all other output lines will be Lo.
23n-line bus Stick diagram ApnAnApn-1An-1An-2Apn-2A’n-1AnA’nAn-1
29System Considerations Lose sight of overall system requirements and restrictionsUse of buses to interconnect subsystems and circuits must always be most carefully considered.Bipolar drivers for Bus LinesBasic arrangements for Bus LinesPower dissipation for CMOS and BiCMOS circuitsCurrent limitationsFurther aspects of Vdd and Vss rail distribution
30Bipolar drivers for Bus Lines Bus structures carrying data and control signals are generally long and connected to and trough a significant number of circuits and subsystemsPropagation of signals may be a slow processThe capacitive load driving properties of bipolar transistors in a BiCMOS process make bipolar drivers an attractive proposition for bus lines
31Basic arrangements for Bus Lines There are three classes of bus- passive ,active and prechargedA passive bus rail is a floating rail to which signals may be connected from drivers through series switches
32In active bus a common pull-up Rp In active bus a common pull-up Rp.u and n-type pull-down transistors or series n-type transistor logic
33The Precharged bus concept The precharged bus approach limits the effects of bus capacitance in that a single pull-up transister whch is turned on only during 2
34Power dissipation for CMOS and BiCMOS Circuits The overall dissipation is composed of two terms:P1 the dissipation due to the leakage current I1 through an ‘off’ transistor. Consequently, for n transistors, we haveP1=n.I1.VddWhere I1=0.1 nA, typically at room temperature.Ps is the dissipation due to energy supplied to charge and discharge the capacitances associated with each switching circuitPs=CL.Vdd2.fTotal power dissipation Pt=P1+PsPower dissipation for bipolar devices can be simply modeled byP=Vcc* IcIc is the current through the device
35Current limitations for Vdd and GND rails Metal migration for high current densities in metal conductorsAluminum conductor threshold valueJth=1 to 2 mA
36Further aspects of Vdd and Vss rail distribution Limitations of distributive rails are:Metal migration imposed current density restrictionsThe IR drop due to rail series resistanceThe series inductance of the rails
37IR drop and series inductance For a parent bus supplying current to other uniformly distributed short bus branches along the length L of the parent bus, then the current at any distance x from the source is given byIx=IL(1-x/L)
38series inductance ∆V=L0 di/dt The transmission line nature of any wiring introduces the possibility of voltage transients due to its self-inductance L0. the transient changes in voltage due to the presence of self-inductance can be modeled by∆V=L0 di/dtdi/dt Is the rate of change of line current