Download presentation

Presentation is loading. Please wait.

Published byLuz Marin Modified over 4 years ago

1
Dynamic and Pass-Transistor Logic Prof. Vojin G. Oklobdzija References (used for creation of the presentation material): 1.Masaki, “ Deep-Submicron CMOS Warms Up to High-Speed Logic ”, IEEE Circuits and Devices Magazine, November 1992. 2.Krambeck, C.M. Lee, H.S. Law, “ High-Speed Compact Circuits with CMOS ”, IEEE Journal of Solid-State Circuits, Vol. SC-13, No 3, June 1982. 3.V.G. Oklobdzija, R.K. Montoye, “ Design-Performance Trade-Offs in CMOS- Domino Logic ”, IEEE Journal of Solid-State Circuits, Vol. SC-21, No 2, April 1986.

2
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design2 References: 4.Goncalves, H.J. DeMan, “ NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Structures ”, IEEE Journal of Solid- State Circuits, Vol. SC-18, No 3, June 1983. 5.L.G. Heller, et al, “ Cascode Voltage Switch Logic: A Differential CMOS Logic Family ”, in 1984 Digest of Technical Papers, IEEE International Solid-State Circuits Conference, February 1984. 6.L.C.M.G. Pfennings, et al, “ Differential Split-Level CMOS Logic for Subnanosecond Speeds ”, IEEE Journal of Solid-State Circuits, Vol. SC-20, No 5, October 1985. 7.K.M. Chu, D.L. Pulfrey, "A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic", IEEE Jouirnal of Solid-State Circuits, Vol. SC-22, No.4, August 1987.

3
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design3 References: Pass-Transistor Logic: 8.S. Whitaker, “ Pass-transistor networks optimize n-MOS logic ”, Electronics, September 1983. 9.K. Yano, et al, “ A 3.8-ns CMOS 16x16-b Multiplier Using Complementary Pass-Transistor Logic ”, IEEE Journal of Solid- State Circuits, Vol. 25, No 2, April 1990. 10.K. Yano, et al, “ Lean Integration: Achieving a Quantum Leap in Performance and Cost of Logic LSIs", Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994. 11.M. Suzuki, et al, “ A 1.5ns 32b CMOS ALU in Double Pass- Transistor Logic ”, Journal of Solid-State Circuits, Vol. 28. No 11, November 1993. 12.N. Ohkubo, et al, “ A 4.4-ns CMOS 54x54-b Multiplier Using Pass-transistor Multiplexer ”, Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1- 4, 1994.

4
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design4 References: 13.V. G. Oklobdzija and B. Duchêne, “Pass-Transistor Dual Value Logic For Low-Power CMOS,” Proceedings of the 1995 International Symposium on VLSI Technology, Taipei, Taiwan, May 31-June 2nd, 1995. 14.F.S. Lai, W. Hwang, “Differential Cascode Voltage Switch with the Pass-Gate (DCVSPG) Logic Tree for High Performance CMOS Digital Systems”, Proceedings of the 1993 International Symposium on VLSI Technology, Taipei, Taiwan, June 2-4, 1995 15.A. Parameswar, H. Hara, T. Sakurai, “A Swing Restored Pass- Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications”, Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994. 16.T. Fuse, et al, “0.5V SOI CMOS Pass-Gate Logic”, Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference, San Francisco February 8, 1996.

5
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design5 Pass-Transistor Logic

6
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design6 Pass-Transistor Logic (a)XOR function implemented with pass-transistor circuit (b)Karnaough map showing derivation of the XOR function (a) (b)

7
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design7 Pass-Transistor Logic General topology of pass- transistor function generator Karnaough map of 16 possible functions that can be realized

8
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design8 Pass-Transistor Logic Function generator implemented with pass- transistor logic

9
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design9 Pass-Transistor Logic Voltage drop does not exceed Vth when there are multiple transistors in the path Threshold voltage drop at the output of the pass- transistor gate

10
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design10 Pass-Transistor Logic Elimination of the threshold voltage drop by: (a)pairing nMOS transistor with a pMOS (b) using a swing-restoring inverter

11
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design11 Complementary Pass-Transistor Logic (CPL)

12
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design12 Basic logic functions in CPL

13
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design13 CPL Logic CPL provides an efficient implementation of XOR function XOR gate Sum circuit

14
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design14 CPL Inverter

15
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design15 Double Pass-Transistor Logic (DPL): XOR/XNOR AND/NAND

16
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design16 Double Pass-Transistor Logic (DPL): XOR One bit full-adder: Sum circuit

17
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design17 Double Pass-Transistor Logic (DPL): The critical path traverses two transistors only (not counting the buffer) DPL Full Adder

18
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design18 Formal Method for CPL Logic Derivation Markovic et al. 2000 ( a)Cover the Karnaugh-map with largest possible cubes (overlapping allowed) (b)Express the value of the function in each cube in terms of input signals (c)Assign one branch of transistor(s) to each of the cubes and connect all the branches to one common node, which is the output of NMOS pass-transistor network

19
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design19 Formal Method for P-T Logic Derivation Complementary function can be implemented from the same circuit structure by applying complementarity principle: Complementarity Principle: Using the same circuit topology, with pass signals inverted, complementary logic function is constructed in CPL. By applying duality principle, a dual function is synthesized: Duality Principle: Using the same circuit topology, with gate signals inverted, dual logic function is constructed. Following pairs of basic functions are dual: AND-OR (and vice-versa) NAND-NOR (and vice-versa) XOR and XNOR are self-dual (dual to itself)

20
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design20 Derivation of P-T Logic Copmplementarity: AND NAND; Duality: AND OR

21
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design21 Derivation of CPL Logic Duality: AND OR NAND NOR Complementarity: AND NAND

22
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design22 Two-Input Function with balanced input load Each input A, B, or A, B has FO=2

23
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design23 Derivation of CPL Logic (a) XOR function Karnaugh map, (b) XOR/XNOR circuit

24
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design24 Synthesis of three-input CPL logic (a) AND function Karnaugh map, (b) AND/NAND circuit

25
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design25 Circuit realization of 3-input AND/NAND function

26
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design26 Double Pass-Transistor Logic (DPL): Synthesis Rules 1. Two NMOS branches can not be overlapped covering logic 1s. Similarly, two PMOS branches can not be overlapped covering logic 0s. 2. Pass signals are expressed in terms of input signals or supply. Every input vector has to be covered with exactly two branches. At any time, excluding transitions, exactly two transistor branches are active (any of the pairs NMOS/PMOS, NMOS/NMOS and PMOS/PMOS are possible), i.e. they both provide output current.

27
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design27 Double Pass-Transistor Logic (DPL): Synthesis Rules Complementarity Principle: Complementary logic function in DPL is generated after the following modifications: Exchange PMOS and NMOS devices. Invert all pass and gate signals Duality Principle: Dual logic function in DPL is generated when: PMOS and NMOS devices are exchanged, and VDD and GND signals are exchanged.

28
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design28 DPL Synthesis: (a) AND function Karnaugh map (b) AND/NAND circuit

29
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design29 DPL Synthesis: OR/NOR circuit

30
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design30 XOR/XNOR in DPL Circuit realization of 2-input XOR/XNOR function in DPL, with balanced input load

31
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design31 DPL Synthesis: AND function Karnaugh map AND/NAND circuit Duality Principle: PMOS and NMOS devices are exchanged, and VDD and GND signals are exchanged: AND OR NAND NOR Complementarit y Principle: Exchange PMOS and NMOS devices. Invert all pass and gate signals AND NAND

32
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design32 DVL Logic Advantage of CPL and DPL were recognized in DVL which attempts to generalize pass-transistor networks and minimize the number of transistors and input loads. Rules: 1.Cover all input vectors that produce “0” at the output, with largest possible cubes (overlapping allowed) and represent those cubes with NMOS devices, with sources connected to GND 2.Repeat step 1 for input vectors that produce “1” at the output and represent those cubes with PMOS devices, with sources connected to V dd 3.Finish with mapping input vectors, not mapped in steps 1 and 2 (overlapping with cubes from steps 1 and 2 allowed) that produce”0” or “1” at the output. Represent those cubes with parallel NMOS (good pull-down) and PMOS (good pull-up) branches, with sources connected to one of the input signals

33
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design33 Two input AND/NAND in DVL Logic Circuit realization of 2-input AND/NAND function in DVL

34
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design34 Two input OR/NOR in DVL Logic Circuit realization of 2-input OR/NOR circuit in DVL XOR/XNOR realization is identical to that of DPL.

35
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design35 Three input AND function in DVL Logic

36
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design36 Three input OR/NOR in DVL Circuit realization of 3-input OR/NOR functions in DVL

37
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design37 Comparison Realization # of input signals Signal termination Trans. Count Output load CMOS910G104S DVL (b)98G + 6S86S DVL (c)97G + 3S74S TABLE I. Realizations of 3-input function F=B’C+ABC’

38
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design38Comparison Realizations of 3-input function F=B’C+ABC’ (a) Standard CMOS, (b) DVL, (c) DVL

39
Fall 2004Prof. V. G. Oklobdzija: High-Performance System Design39 Conclusion General rules for synthesizing logic gates in three representative pass-transistor techniques were shown. An algorithmic way for generation of various circuit topologies (complementary and dual circuits) is discussed. Generation of circuits with balanced input loads is suitable for library based designs is possible if complementarity and commutative principles are applied. This lays the foundation for development of computer aided design (CAD) tools capable of generating fast and power-efficient pass-transistor logic.

Similar presentations

Presentation is loading. Please wait....

OK

Static CMOS Logic Seating chart updates

Static CMOS Logic Seating chart updates

© 2018 SlidePlayer.com Inc.

All rights reserved.

To make this website work, we log user data and share it with processors. To use this website, you must agree to our Privacy Policy, including cookie policy.

Ads by Google