1. High Speed Digital Design Project SpaceWire Router By: Asaf Bercovich & Oren Cohen Advisor: Mony Orbach Semester: Winter 2007/2008 2-Semester Project Date: 7 January 2008 Midterm Presentation

2. Project Goal Designing a SpaceWire Switch Core (Router) compatible to ECSS-E-50-12A Standard. The design will be coded and simulated using Xilinx development enviroment and implemented onto a Xilinx VirtexII-Pro FPGA. Designing a SpaceWire Switch Core (Router) compatible to ECSS-E-50-12A Standard. The design will be coded and simulated using Xilinx development enviroment and implemented onto a Xilinx VirtexII-Pro FPGA.

3. System Topology Router

4. System Topology Router PORT Full duplex Low latency Point-to-point Wormhole Routing Asynchronous communication Automatic failover 800 Mb/s of Traffic Total

5. SpaceWire Characters There are only 5 Characters: FCT – “Flow Control Token" ESC – “Escape” FCT – “Flow Control Token" ESC – “Escape” EOP – “End Of Packet” EEP – “End of Packet with Error” EOP – “End Of Packet” EEP – “End of Packet with Error” NCHAR – “Normal Character”

6. The SpaceWire Port Entity Architecture Receiver Port Controller Din Sin Dout Sout Clock Reset RX DATA / Control TX DATA / Control Link Start / Link Disable Link Start / Link Disable State Machine TX Clock Transmitter FIFO RX_CLOCK FIFO Write Ready Read Ready Write

7. Receiver The SpaceWire Port Architecture Port Controller Din Sin Dout Sout Clock Reset RX DATA / Control TX DATA / Control Link Start / Link Disable Link Start / Link Disable State Machine TX Clock Transmitter FIFO RX_CLOCK FIFO Write Ready Read Ready Write

8. Internal Signals Transmitter Receiver Port Controller (State Machine) Port Controller (State Machine) RESET Send NULLs Send FCTs Send N-Chars Send Time-Codes GotFCT Got Time-Code GotN-Char GotNULL CreditError RX_Err RESET

9. Port Controller RX_Err ‘1’ D Q Flip Flop R Synchronization Example Asynchronous Reset D Q Flip Flop R D Q R Controller’s Clock Synchronizer Controller Logic

10. Receiver The SpaceWire Port Architecture Port Controller Din Sin Dout Sout Clock Reset RX DATA / Control TX DATA / Control Link Start / Link Disable Link Start / Link Disable State Machine TX Clock Transmitter FIFO RX_CLOCK FIFO Write Ready Read Ready Write

11. Shift Register Logic Port Transmitter “The Factory” Controller Dout Sout SpaceWire Character TX Clock DS Encoder TX DATA Control Signa ls Logic

12. Receiver The SpaceWire Port Architecture Port Controller Din Sin Dout Sout Clock Reset RX DATA / Control TX DATA / Control Link Start / Link Disable Link Start / Link Disable State Machine TX Clock Transmitter FIFO RX_CLOCK FIFO Write Ready Read Ready Write

13. Port Receiver Shift Register Sequence Detector + Data Extraction MEM Error Reporting RX_DATA to FIFO RX Clock Recovery Din Sin Rx Clock Din

14. RX Clock Recovery D S RX_CLOCK Version I – XOR Gate D S RX_CLOCK

15. RX Clock Recovery S RX_CLOCK Version II - Quad Data Rate Flip Flop D S D Q RX_CLOCK D

16. RX Clock Recovery Version III – Three DDR Flip Flops & XOR Gate S RX_CLOCK D

17. RX Clock Recovery Version III – Three DDR Flip Flops & XOR Gate D D Q DDR FF S D Q RX_CLOCK D Q DDR FF better RX_CLOCK

18. Project Milestones 8-14/1/08 – Assimilation of FIFOs into Port’s architecture. 15-21/1/08 – Checking feasibility for 200 MHz work frequency (using DCM module). 22/1–11/2/08 – Testing & Stabilization of Port’s final design. 12/2-25/2/08- Gathering information about routing with SpaceWire. 8-14/1/08 – Assimilation of FIFOs into Port’s architecture. 15-21/1/08 – Checking feasibility for 200 MHz work frequency (using DCM module). 22/1–11/2/08 – Testing & Stabilization of Port’s final design. 12/2-25/2/08- Gathering information about routing with SpaceWire. Semester Goal – Port Completion

19. References ECSS-E-50-12A - 24 January 2003