1. EEL4712 Digital Design
(MIPS Processor)

2. Stored Program Instructions and data stored in memory.
Only difference between two applications (for example, a text editor and a video game), is the sequence of instructions.
To run a new program:
No rewiring required
Simply store new program in memory
The processor hardware executes the program:
fetches (reads) the instructions from memory in sequence
performs the specified operation
The program counter (PC) keeps track of the current instruction.

3. High-level Programs to Instructions
Therefore with the help of a compiler (and assembler), to run applications all we need is a means to interpret (or “execute”) machine instructions.
Usually the application calls on the operating system and libraries to provide special functions.

4. Architecture Layers
Architecture: the programmer’s view of the computer
Defined by instructions (operations) and operand locations
Microarchitecture: how to implement an architecture in hardware
The microarchitecture is built out of “logic” circuits and memory elements (what we learnt so far :D).
All logic circuits and memory elements are implemented in the physical world with transistors.

5. Interpreting Instructions to Machine Codes
Start with opcode
Opcode tells how to parse the remaining bits
If opcode is all 0’s
R-type instruction
Function bits tell what instruction it is
Otherwise
Opcode tells what instruction it is
☼A processor is a machine code interpreter build in hardware!

6. Processor
A processor execute a set of instructions of a computer program by performing the basic arithmetic, logic, controlling, input/output operations specified by the instructions.
Ref:
Block diagram of a basic uniprocessor-CPU computer. Black lines indicate data flow, whereas red lines indicate control flow; arrows indicate flow directions.

7. MIPS Processor
MIPS: Microprocessor without Interlocked Pipelined Stages C P U R e g i s t r $ 3 1 A h m c M u l p y d v L o H ( F ) n B a V S E
Prog. Counter
Logic unit
Control

8. MIPS Instructions Here is a subset of MIPS instructions:
R-type instructions: and, or, add, sub, …
Memory instructions: lw, sw
Branch instructions: beq

9. MIPS State Elements
Determines everything about the execution status of a processor:
PC (Program Counter) register
32 registers
Memory
Note: for these state elements, clock is used for write but not for read (asynchronous read, synchronous write).

10. Instruction Memory Instructions are bits Programs are stored in memory
to be read or written just like data
Fetch & Execute Cycle
Instructions are fetched and put into a special register
Bits in the register "control" the subsequent actions
Fetch the “next” instruction and continue
Processor
Memory
Instructions/Data

11. Memory Organization
Viewed as a large, single-dimension array, with an address.
A memory address is an index into the array
"Byte addressing" means that the index points to a byte of memory.
Bytes are nice, but most data items use larger "words"
For MIPS, a word is 32 bits or 4 bytes.
(We will discuss it later) 1 2 3 4 5 6
...
8 bits of data

12. Registers vs. Memory
Arithmetic instructions operands must be registers,
only 32 registers provided
Compiler associates variables with registers
What about programs with lots of variables
Processor
I/O
Control
Datapath
Memory
Input
Output

13. MIPS Memory Organization
Bytes are nice, but most data items use larger "words"
For MIPS, a word is 32 bits or 4 bytes.
232 bytes with byte addresses
from 0 to 232-1
230 words with byte addresses
0, 4, 8,
Words are aligned

14. MIPS Alignment
MIPS restricts memory accesses to be aligned as follows:
32-bit word has to start at byte address that is multiple of 4;
32-bit word at address 4n includes four bytes with addresses 4n, 4n+1, 4n+2, and 4n+3.
16-bit half word has to start at byte address that is multiple of 2;
16-bit word at address 2n includes two bytes with addresses 2n and 2n+1.

15. MIPS Registers CPU 32-bit general purpose registers -GPRS (r0-r31)
r0 has fixed value of zero. Attempt to writing into r0 is not illegal, but its value will not change;
Two 32-bit registers –
Hi & Lo, hold results of integer multiply and divide
32-bit program counter - PC

16. MIPS Arithmetic All instructions have 3 operands
Operand order is fixed (destination first) Example: C code: a = b + c MIPS ‘code’: add a, b, c “The natural number of operands for an operation like addition is three…requiring every instruction to have exactly three operands, no more and no less, conforms to the philosophy of keeping the hardware simple”

17. MIPS Arithmetic Design Principle: simplicity favors regularity.
Of course this complicates some things... C code: a = b + c + d; MIPS code: add a, b, c add a, a, d
Operands must be registers, only 32 registers provided
Each register contains 32 bits

18. How to Design a Processor: step-by-step
1. Analyze instruction set architecture (ISA) ⇒ datapath requirements
meaning of each instruction is given by the data transfers (register transfers)
datapath must include storage element for ISA registers – datapath must support each data transfer
2. Select set of datapath components and establish clocking methodology
3. Assemble datapath meeting requirements
4. Analyze implementation of each instruction to determine setting of control points that effects the data transfer.
5. Assemble the control logic.

19. MIPS Instructions The different fields are:
op: operation (“opcode”) of the instruction
rs, rt, rd: the source and destination register specifiers
shamt: shift amount
funct: selects the variant of the operation in the “op” field
address / immediate: address offset or immediate value
target address: target address of jump instruction

20. Instruction types add, sub, or, slt lw, sw beq addu rd,rs,rt
subu rd,rs,rt
lw, sw
lw rt,rs,imm16
sw rt,rs,imm16
beq
beq rs,rt,imm16

21. MIPS Instructions (More Details)
32-bit fixed format instruction and 3 formats;
Register
register and register
immediate computational instructions;
single address mode for load/store instructions:
register content + offset (called base addressing);
simple branch conditions;
branch instructions use PC relative addressing;
branch address = [PC] ×offset
jump instructions with:
28-bit addresses (jumps inside 256 megabyte regions),
absolute 32-bit addresses.

22. Register Transfer Descriptions
All start with instruction fetch:
{op , rs , rt , rd , shamt , funct} ← IMEM[ PC ] OR
{op , rs , rt , Imm16} ← IMEM[ PC ] THEN

23. Microarchitecture Multiple implementations for a single architecture:
Single-cycle
Each instruction executes in a single clock cycle.
Multicycle
Each instruction is broken up into a series of shorter steps with one step per clock cycle.
Pipelined (variant on “multicycle”)
Each instruction is broken up into a series of steps with one step per clock cycle
Multiple instructions execute at once.

24. CPU clocking
Single Cycle CPU: All stages of an instruction are completed within one long clock cycle.
The clock cycle is made sufficient long to allow each instruction to complete all stages without interruption and within one cycle.

25. CPU Clocking
Multiple-cycle CPU: Only one stage of instruction per clock cycle.
The clock is made as long as the slowest stage

26. MIPS State Elements
Determines everything about the execution status of a processor:
PC (Program Counter) register
32 registers
Memory
Note: for these state elements, clock is used for write but not for read (asynchronous read, synchronous write).

27. Single-Cycle Datapath: lw fetch
First Consider executing load operation
R[rt] ← DMEM[ R[rs] + sign_ext(Imm16)]
STEP 1: Fetech the instruction

28. Single-Cycle Datapath: lw register read
R[rt] ← DMEM[ R[rs] + sign_ext(Imm16)]
STEP 2: Read source operands from register file

29. Single-Cycle Datapath: lw immediate
R[rt] ← DMEM[ R[rs] + sign_ext(Imm16)]
STEP 3: Sign-extend the immediate

30. Single-Cycle Datapath: lw address
R[rt] ← DMEM[ R[rs] + sign_ext(Imm16)]
STEP 4: Compute the memory address

31. Single-Cycle Datapath: lw memory read
R[rt] ← DMEM[ R[rs] + sign_ext(Imm16)]
STEP 5: Read data from memory and write it back to register file

32. Single-Cycle Datapath: lw PC increment
PC  PC + 4
STEP 6: Determine the address of the next
instruction

33. Single-Cycle Datapath: sw
DMEM[ R[rs] + sign_ext(Imm16) ] ← R[rt]
Write data in rt to memory

34. Single-Cycle Datapath: R-type Instruction
R[rd] ← R[rs] op R[rt]
Read from rs and rt
Write ALUResult to register file
Write to rd (instead of rt)

35. Single-Cycle Datapath: R-type instructions
R[rd] ← R[rs] op R[rt]
Read from rs and rt
Write ALUResult to register file
Write to rd (instead of rt)

36. Single-Cycle Datapath: beq
Execution of branch instructions

37. Single-Cycle Datapath: beq
if ( R[rs] == R[rt] ) then PC ← PC {sign_ext(Imm16), 00}
Determine whether values in rs and rt are equal
Calculate branch target address: BTA = (sign-extended immediate << 2) + (PC+4)
PCSrc = 1 branches to
PC+4+(offset x 4)
PCSrc = 0
Continues to PC+4
Multiply constant by 4 to get offset
We need a second adder, since the ALU is already doing subtraction for beq

38. References

39. Questions?