1. Computer Architecture CSE 3322 Lecture 2 NO CLASS MON Sept 1 Course WEB SITE crystal.uta.edu/~jpatters

2. Computer Generations Overview GenerationTechnologyPrinciple Product Adj Price/ Perfomance 0 1945-50 RelaysResearch Model NA

3. Computer Generations Overview GenerationTechnologyPrinciple Product Adj Price/ Perfomance 0 1945-50 RelaysResearch Model NA 1 1950-59 Vacuum Tubes Mag Core Commercial Monsters 1 (UNIVAC )

4. Computer Generations Overview GenerationTechnologyPrinciple Product Adj Price/ Perfomance 0 1945-50 RelaysResearch Model NA 1 1950-59 Vacuum Tubes Mag Core Commercial Monsters 1 (UNIVAC ) 2 1960-68 Transistors Mag Core Most Large Corp/Univ 318

5. Computer Generations Overview GenerationTechnologyPrinciple Product Adj Price/ Perfomance 0 1945-50 RelaysResearch Model NA 1 1950-59 Vacuum Tubes Mag Core Commercial Monsters 1 (UNIVAC ) 2 1960-68 Transistors Mag Core Most Large Corp/Univ 318 3 1969-77 Integrated Circuits DRAM Minicomputer 13K

6. Computer Generations Overview GenerationTechnologyPrinciple Product Adj Price/ Perfomance 0 1945-50 RelaysResearch Model NA 1 1950-59 Vacuum Tubes Mag Core Commercial Monsters 1 (UNIVAC ) 2 1960-68 Transistors Mag Core Most Large Corp/Univ 318 3 1969-77 Integrated Circuits DRAM Minicomputer 13K 4 1978- VLSI DRAM Personal Computer 239M

7. Technological Growth DRAM Growth: 4X Capacity Every 3 Years

8. Technological Growth DRAM Growth: 4X Capacity Every 3 Years Workstation Performance Improvement: 54% per year or 2X every18 months

9. Technological Growth DRAM Growth: 4X Capacity Every 3 Years Workstation Performance Improvement: 54% per year or 2X every18 months Disk Drive Growth: Capacity More than 2x every year

10. Technological Growth DRAM Growth: 4X Capacity Every 3 Years Workstation Performance Improvement: 54% per year or 2X every18 months Disk Drive Growth: Capacity More than 2x every year All Continue to Drive Price /Performance Improvements

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12. Five Components of Computers Input Output Memory Control Datapath Processor

13. Instruction Set Design Key Element in the Architecture –Function, Cost, Performance, etc.

14. Instruction Set Design Key Element in the Architecture –Function, Cost, Performance, etc. Typical Machine Instructions –Data Transfers ( reg-reg, reg-mem, mem-reg) –Arithmetic (add, subtract, multiply) –Logic & String (boolean, bit manipulations) –Program Control ( branches, jumps) –Input/Output Operations

15. Instruction Set Design Study the MIPS Architecture

16. Instruction Set Design Study the MIPS Architecture A WORD is 32 bits or 4 bytes wide for Registers and Memory

17. Instruction Set Design Study the MIPS Architecture A WORD is 32 bits or 4 bytes wide for Registers and Memory Each byte has Memory Address starting at 0

18. Instruction Set Design Study the MIPS Architecture A WORD is 32 bits or 4 bytes wide for Registers and Memory Each byte has Memory Address starting at 0 WORD Addresses start at 0 and are multiples of 4

19. Instruction Set Design Study the MIPS Architecture A WORD is 32 bits or 4 bytes wide for Registers and Memory Each byte has Memory Address starting at 0 WORD Addresses start at 0 and are multiples of 4 Big-endian Byte 0, Byte 1, Byte 2, Byte 3 Little-endian Byte 3, Byte 2, Byte 1, Byte 0

20. Instruction Set Design Study the MIPS Architecture A WORD is 32 bits or 4 bytes wide for Registers and Memory Each byte has Memory Address starting at 0 WORD Addresses start at 0 and are multiples of 4 Big-endian Byte 0, Byte 1, Byte 2, Byte 3 Little-endian Byte 3, Byte 2, Byte 1, Byte 0 32 Registers with Conventions on Use

21. b3 b2 b1 b0 b7 b6 b5 b4 b11 b10 b9 b8 bM 0 1 31 Memory Registers N 8 4 0 32 bits

22. MIPS Assembly Instructions Instruction Example Meaning add add $s1, $s2, $s3 $s1 = $s2 + $s3 subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 $s1, $s2, $s3, … are registers. The $ indicates a Register in the MIPS Assembly Language

23. MIPS Assembly Instructions Instruction Example Meaning add add $s1, $s2, $s3 $s1 = $s2 + $s3 subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 $s1, $s2, $s3, … are registers. The $ indicates a Register in the MIPS Assembly Language Also $s2 + $s3 $s1

24. Machine Instruction Format Instr Format op rs rt rd shamt funct add R 0 reg reg reg 0 32 sub R 0 reg reg reg 0 34 bits 6 5 5 5 5 6 R Type Instruction op : opcode rd : register destination operand rs : reg source 1 operand shamt : shift amount rt : reg source 2 operand funct : function code – variant of operation

25. Machine Instruction Format Instr Format op rs rt rd shamt funct add R 0 18 8 8 0 32 bits 6 5 5 5 5 6 add $t0, $s2, $t0 where $t0 is reg 8, $s2 is reg 18 $t0 = $s2 + $t0

26. Machine Instruction Format Instr Format op rs rt rd shamt funct add R 0 18 8 8 0 32 bits 6 5 5 5 5 6 Example of Machine Language Instruction 000000 10010 01000 01000 00000 100000 0 18 8 8 0 32 op rs rt rd shamt funct add $t0, $s2, $t0 where $t0 is reg 8, $s2 is reg 18 $t0 = $s2 + $t0

27. MIPS Assembly Instructions Instruction Example Meaning load word lw $s1, 300 ($s2) $s1 = Mem[$s2+300] store word sw $s1, 300 ($s2) Mem[$s2+300] = $s1 $s1, $s2, $s3, … are registers 300 is a constant

28. Machine Instruction Format Instr Format op rs rt address/ immediate lw I 35 reg reg constant sw I 43 reg reg constant bits 6 5 5 16 I Type Instruction op : opcode rs : reg address operand rt : reg destination or source operand lw $s1, 300 ($s2)

29. C statement: A[i] = h + A[i] A[i] & h are integers where A is an array with base in $s3 h is in $s1 i is in $s2

30. A[i] A[3] A[2] A[1] A[0] Base + 4 * i Base + 12 Base + 8 Base + 4 Base Words in an Array in memory are 4 bytes apart, so the Address increments by 4. C statement: A[i] = h + A[i], A[i] & h are integers where A is an array with base in $s3 h is in $s1 i is in $s2

31. Compiles into assembly code: # denotes comments C statement: A[i] = h + A[i] where A is an array with base in $s3 h is in $s1 i is in $s2

32. Compiles into assembly code: # denotes comments # Compute Address of A[i]: Base + 4*i C statement: A[i] = h + A[i] where A is an array with base in $s3 h is in $s1 i is in $s2

33. Compiles into assembly code: # Compute Address of A[i ]: Base + 4*i add $t1, $s2, $s2 # Temp reg $t1 = i + i =2i add $t1, $t1, $t1 # Temp reg $t1 = 2i +2i = 4i C statement: A[i] = h + A[i] where A is an array with base in $s3 h is in $s1 i is in $s2

34. Compiles into assembly code: # Compute Address of A[i ]: Base + 4*i add $t1, $s2, $s2 # Temp reg $t1 = i + i =2i add $t1, $t1, $t1 # Temp reg $t1 = 2i +2i = 4i add $t1, $t1, $s3# $t1 = address of A[i] C statement: A[i] = h + A[i] where A is an array with base in $s3 h is in $s1 i is in $s2

35. Compiles into assembly code: # Compute Address of A[i ]: Base + 4*i add $t1, $s2, $s2 # Temp reg $t1 = i + i =2i add $t1, $t1, $t1 # Temp reg $t1 = 2i +2i = 4i add $t1, $t1, $s3# $t1 = address of A[i] # Compute the new A[i] lw $t2, 0($t1)# Temp reg $t2 = A[i] C statement: A[i] = h + A[i] where A is an array with base in $s3 h is in $s1 i is in $s2

36. Compiles into assembly code: # Compute Address of A[i] : Base + 4*i add $t1, $s2, $s2 # Temp reg $t1 = i + i =2i add $t1, $t1, $t1 # Temp reg $t1 = 2i +2i = 4i add $t1, $t1, $s3# $t1 = address of A[i] # Compute the new A[i] lw $t2, 0($t1)# Temp reg $t2 = A[i] add $t2, $t2, $s1# $t2 = A[i] + h C statement: A[i] = h + A[i] where A is an array with base in $s3 h is in $s1 i is in $s2

37. Compiles into assembly code: # Compute Address of A[i] : Base + 4*i add $t1, $s2, $s2 # Temp reg $t1 = i + i =2i add $t1, $t1, $t1 # Temp reg $t1 = 2i +2i = 4i add $t1, $t1, $s3# $t1 = address of A[i] # Compute the new A[i] lw $t2, 0($t1)# Temp reg $t2 = A[i] add $t2, $t2, $s1# $t2 = A[i] + h sw $t2, 0($t1)# Store $t2 into A[i] C statement: A[i] = h + A[i] where A is an array with base in $s3 h is in $s1 i is in $s2

38. lw $t2, 0($t1)# Temp reg $t2 = A[i] add $t2, $t2, $s1# $t2 = A[i] + h sw $t2, 0($t1)# Store $t2 into A[i] $s1~17, $t1~9, $t2~10 Translate to MIPS Machine language using decimal op rs rt rd address/shamt funct

39. lw $t2, 0($t1)# Temp reg $t2 = A[i] add $t2, $t2, $s1# $t2 = A[i] + h sw $t2, 0($t1)# Store $t2 into A[i] $s1~17, $t1~9, $t2~10 Translate to MIPS Machine language using decimal op rs rt rd address/shamt funct 35

40. lw $t2, 0($t1)# Temp reg $t2 = A[i] add $t2, $t2, $s1# $t2 = A[i] + h sw $t2, 0($t1)# Store $t2 into A[i] $s1~17, $t1~9, $t2~10 Translate to MIPS Machine language using decimal op rs rt rd address/shamt funct 35 9 10 0

41. lw $t2, 0($t1)# Temp reg $t2 = A[i] add $t2, $t2, $s1# $t2 = A[i] + h sw $t2, 0($t1)# Store $t2 into A[i] $s1~17, $t1~9, $t2~10 Translate to MIPS Machine language using decimal op rs rt rd address/shamt funct 35 9 10 0 0 10 17 10 0 32

42. lw $t2, 0($t1)# Temp reg $t2 = A[i] add $t2, $t2, $s1# $t2 = A[i] + h sw $t2, 0($t1)# Store $t2 into A[i] $s1~17, $t1~9, $t2~10 Translate to MIPS Machine language using decimal op rs rt rd address/shamt funct 35 9 10 0 0 10 17 10 0 32 43 9 10 0

43. lw $t2, 0($t1)# Temp reg $t2 = A[i] add $t2, $t2, $s1# $t2 = A[i] + h sw $t2, 0($t1)# Store $t2 into A[i] $s1~17, $t1~9, $t2~10 Translate to MIPS Machine language using decimal op rs rt rd address/shamt funct 35 9 10 0 0 10 17 10 0 32 43 9 10 0 Translate to MIPS Machine language using binary 100011 01001 01010 0000000000000000

44. lw $t2, 0($t1)# Temp reg $t2 = A[i] add $t2, $t2, $s1# $t2 = A[i] + h sw $t2, 0($t1)# Store $t2 into A[i] $s1~17, $t1~9, $t2~10 Translate to MIPS Machine language using decimal op rs rt rd address/shamt funct 35 9 10 0 0 10 17 10 0 32 43 9 10 0 Translate to MIPS Machine language using binary 100011 01001 01010 0000000000000000 000000 01010 10001 01010 00000 100000

45. lw $t2, 0($t1)# Temp reg $t2 = A[i] add $t2, $t2, $s1# $t2 = A[i] + h sw $t2, 0($t1)# Store $t2 into A[i] $s1~17, $t1~9, $t2~10 Translate to MIPS Machine language using decimal op rs rt rd address/shamt funct 35 9 10 0 0 10 17 10 0 32 43 9 10 0 Translate to MIPS Machine language using binary 100011 01001 01010 0000000000000000 000000 01010 10001 01010 00000 100000 101011 01001 01010 0000000000000000

46. Two Key Principles Instructions are represented the same as numbers Programs are stored in memory to be read or written just like numbers

47. Two Key Principles Instructions are represented as numbers Programs are stored in memory to be read or written just like numbers This is the Stored Program Concept –Programs can operate on other programs!