CSE 140 Lecture 12 Combinational Standard Modules CK Cheng CSE Dept. UC San Diego 1

Part III. Standard Modules Interconnect Modules: 1. Decoder, 2. Encoder 3. Multiplexer, 4. Demultiplexer 2

Multiplexer Definition Logic Diagram Application 3

4 Interconnect: Decoder, Encoder, Mux, DeMux Processors Decoder: Decode the address to assert the addressed device Mux: Select the inputs according to the index addressed by the control signals P1 Memory Bank Mux P2 Pk Demux Decoder Mux Data Address Address k Address 2 Address 1 Data 1 Data k Arbiter n n-m m 2m2m

iClicker: Multiplexer Definition A.A device that interleaves two or more activities B.A communications device that combines several signals for transmission over a single medium C.A logic circuit that sends one of several inputs out over a single output channel. D.The circuit that uses a common communications channel for sending two or more messages or signals. E.All of the above 5

3. Mux (Multiplexer) Definition: A digital module that selects one of data inputs according to the binary address of the selector. Description If E = 1 y = D i where i = (S n-1,.., S 0 ) Else y = 0 E y D 2 n -1 -D 0 (Data input) S n-1,0 (Selector or Address) 6

Multiplexer (Mux): Definition Selects between one of N inputs to connect to the output. log 2 N-bit select input – control input 7 E: Enable y: Output S: Selector or Address D0D0 D1D1 0 1 Data input

8 PI Q: What is the output of the following MUX? A.0 B.1 C.Can’t say E =1 y S=

Multiplexer (Mux): Definition Selects between one of N inputs to connect to the output. log 2 N-bit select input – control input Example: 2:1 Mux 9

Multiplexer Definition: Example En y S1S1 S0S0 D0D0 D1D1 D2D2 D3D S1S1 S0S0 y

Multiplexer Definition: Example E y S1S1 S0S0 D0D0 D1D1 D2D2 D3D E=1: If D 0 = 0 and S 1 S 0 = 00 => y = 0 If D 0 = 1 and S 1 S 0 = 00 => y = 1 11

Multiplexer: Logic Diagram Logic gates –Sum-of-products form Tristates –For an N-input mux, use N tristates –Turn on exactly one to select the appropriate input 12

Multiplexer Application Mux for a Boolean function with truth table as input 13

Multiplexer: Application 14

Multiplexer Application: universal set {Mux} We use selector to decompose the function into smaller functions (less number of variables), which follows Shannon’s expansion. We simplify the decomposed functions using K-map, which follows consensus theorem. 15

Multiplexer Application: universal set {Mux} Example 1: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with an 8-input Mux. Id a b c f En y a b c S2S2 S1S1 S0S

E y a b S1S1 S0S Example 2: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 4-input Muxes. 17 a0011a0011 b0101b0101 c = 0 c = 1 D (c) D 0 (c) = D 1 (c) = D 2 (c) = D 3 (c) =

a01a D (b,c) D 0 (b,c) D 1 (b,c) E 0 1 a y Example 3: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 2- input Muxes. 18

a01a D (b,c) D 0 (b,c) D 1 (b,c) E b’b’ 0 1 a y D 0 (b,c) = b’D 1 (b,c) = bc c b c b Example 3: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 2- input Muxes. 19 D 1 (b,c)

b01b01 c = 0 0 c = l 1 (0) = 0 l 1 (c) = c E b’b’ 0 1 a y Example 3: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 2- input Muxes. 20

D 1 (b,c) b01b01 c = 0 0 c = l 1 (0) = 0 l 1 (c) = c E E b’b’ 0 1 a b y c Example 3: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 2- input Muxes. 21

Example 4: Given f (a,b,c) = Σm (0,2,4,7) + Σd(3,5), implement with 2- input Muxes f a bc D 0 (b,c) D 1 (b,c) E 0 1 a y D 0 (b,c) D 1 (b,c)

4. Demultiplexers E x Control Input 23

4. Demultiplexers E x y 2 n -1 -y 0 S(n-1,0) Control Input y i = x if i = (S n-1,.., S 0 ) & E=1 y i = 0 otherwise 24

25 Shifters Logical shifter: shifts value to left or right and fills empty spaces with 0’s –Ex: >> 2 = –Ex: << 2 = Arithmetic shifter: same as logical shifter, but on right shift, fills empty spaces with the old most significant bit (msb). –Ex: >>> 2 = –Ex: <<< 2 = Rotator: rotates bits in a circle, such that bits shifted off one end are shifted into the other end –Ex: ROR 2 = –Ex: ROL 2 = 00111

Shifter Can be implemented with a mux s d yiyi E x i+1 x i-1 xixi s d xnxn x0x0 x -1 x n-1 y n -1 y0y0 E s / n l / r y i = x i-1 if E = 1, s = 1, and d = L = x i+1 if E = 1, s = 1, and d = R = x i if E = 1, s = 0 = 0 if E = 0

27 Shifter Design

Barrel Shifter O or 1 shift O or 2 shift O or 4 shift x s0s0 s1s1 s2s2 y 0 1 shift

29 Shifters as Multipliers and Dividers A left shift by N bits multiplies a number by 2 N –Ex: << 2 = (1 × 2 2 = 4) –Ex: << 2 = (-3 × 2 2 = -12) The arithmetic right shift by N divides a number by 2 N –Ex: >>> 2 = (8 ÷ 2 2 = 2) –Ex: >>> 2 = (-16 ÷ 2 2 = -4)