3 Sep 2009SLM1 of 12 SLM performance and limitations based on HW tests

3 Sep 2009SLM2 of 12 HW test in lab Emulates 4 15 kHz rate = ~46 MB/s CPD events per Burst PC =>Start of Burst PC <= End of Burst Burst takes ~8.8s 76 LVDS 10 MHz

3 Sep 2009SLM3 of 12 SLMhwtest CERN-NICE XP program made by Henk Boterenbrood of NIKHEF. Very useful for debugging the FPGA. 4 different hardware patterns are checked and result is written into a log file.

3 Sep 2009SLM4 of 12 Results of HW test 2 super events lost because of timeout limits. No bit, word or address errors. “Fast” CPU 1/2 speed of “Fast” CPU

3 Sep 2009SLM5 of 12 Check with Ethereal what is happening on the Ethernet (PC interface)

3 Sep 2009SLM6 of 12 “Prog + PC→SLM”= 266± 2954 µs PC→SLM=190 ± 8 µs? 0.49s The Ethereal program used to measure Ethernet speed Rate 6176 bytes/456 µs = ~13 MB/s

3 Sep 2009SLM7 of 12 RX from PC TX SLM reply Rx = 64 bytes resp. Tx =6172 bytes Oscilloscope used to measure the RX TX Ethernet ! Rate = 54 MB/s SLM overhead

3 Sep 2009SLM8 of 12 SLM FPGA overhead

3 Sep 2009SLM9 of 12 Example Readout limitations of the SLM Reading of one CPD super event = 6144 bytes ns 32ns 166 MB/s 125 MB/s If PC could send SLM rate = 54 MB/s ev 75 MB/s SRAM between DDR2 and MAC FIFO is needed! Extra 37 µs SLM FPGA PC

3 Sep 2009SLM10 of 12 Example response time for PING Rate = bytes

3 Sep 2009SLM11 of 12 4x15 MB/s 900 MB/s 750 MB/s 2 GB/s Peak Test Event size 6144B / 135 µs Rate 46 MB/s ns TYP Rate 83 MB/s Input Limitations of the SLM with 4 CPDs Because dual port SRAM SLM FPGA

3 Sep 2009SLM12 of 12 Summary HW tests of SLM Input rate from CPD = 46 MB/s (CPD is limiting) SLM inherent output rate = 54 MB/s (PC is limiting) Max readout rate at the test with a dual core NICE XP) = 13 MB/s but varies a lot due other PC activities (see example = ~0.5 s for one event) Two time-outs for 5 * 10 9 CPD super events (but the events are still in the DDR2 so could be recovered with better method)

3 Sep 2009SLM13 of 12 Extra slides Bad and Good points SLM uses 3 IP blocks (2 encrypted commercial) –DDR2 (takes a lot of I/O, R/W simultaneously? Bad doc!) –MAC (Gigabit Ethernet Controller) (FIFO?) –LVDS (CPD interface) (Takes a lot of I/O space, no outputs close to LVDS because of noise pickup!) 7 different power supplies 3.3V, 2.5V, 1.8V, D1.2V, A1.2V, 0.8V, (-2.5V) we use the ELMB to monitor them all. Three Clocks –2x125 MHz (MAC,DDR2) 31 MHz (MAC) –Worst case internal chip delays = 10 ns Power and Cost of Cyclone II $125 as compared to eg. Stratix II $1457

3 Sep 2009SLM14 of 12 Example DDR2 interface uses a lot of very special I/O pins

3 Sep 2009SLM15 of 12 Example DDR2 I/Os results

3 Sep 2009SLM16 of 12 SLM FPGA usage