WP5 – Wirespeed Photonic Firewall Validation Start M27, finish M41(tbc) CIP now lead Description of Work –Establish test bed suitable to validated the optical firewall. –Configure the testbed to simulate and detect a security threat and confirm the operation of the application/ firmware interface and the firmware/optical interface Generate security threat ~ eg (D)DoS attack Route optical packets at wirespeed in response to the threat away from the IP router and into an intercept path. –Establish performance metrics of the optical firewall both at the levels of optical perfomance and algorithm implementation. Speed and accuracy of response of the physical hardware at 40Gbit/s –Comparison of modelled performance benefits of implementing security algorithms in the optical domain from WP3 with measured performance

WP5 – Wirespeed Photonic Firewall Validation DeliverableTitledateRevised D5.2Report on the firewall response to a simulated security attack M34M40 D5.3Report on the overall performance of the firewall M34M40

WISDOM Demonstrator – CIP Activity Proposal –Use software defined patterns to check optics –Configure software to measure packet loss rate –Verifies optical subsystems –May be used for other security applications (e.g. DoS)

Block Diagram Integrated Pattern Match (latency ~ 16 x 6ns) = 96ns Target Block of 16 40G ~ 100ns 2 x 2 switch Match ? No match Match Realtime scope PC Reconfigure target ? Correlate Matched packets With target & data sequence Data sequence Length (?) 128Mb x 25ps = 3.2ms = blocks Stage #1

Pattern Match Rx Low speed Rx to detect whether pattern has been matched or not –One ‘1’ in pattern frame (~100ns), or not Tested existing OC-3 (155Mb/s) Rx –Epitaxx ERM504 –Equivalent part JDSU EDR512

Pattern Match Rx Should be able to use simple electronics with Rx to detect pattern match (?) Logic input required for 2x2 switch eval board Can also use on O/P of 2x2 switch for match/no-match signal to PC

Pattern Generator Options –Rent equipment (BT) SHF 12100B 40GHz optical pulse train 40Gb/s modulator (Tyndall ?) + 40Gb/s RF amplifier –May also have to use 10MHz EAM to improve optical ER because of large block duty cycle (0.4ns every 100ns) Pre-load blocks of 16 40G in pattern generator software

Other Equipment Avanex eval boards –Should have enough boards for demo –Avanex supplying design information CIP devices –Additional packaged 2x2 switch required PC –GPIB, Labview, A/D Card Additional electrical pattern generators for synchronisation RF clock sources (10GHz, 40GHz)

Plan B Demonstrator Risks –Fully integrated devices do not work –Devices do not operate at 40Gb/s Optical memory results ? –Hire of 40G pattern gen Possible options –Reduce bit-rate –Part-fibre setup Need to decide fall-back option