1. ©2006 Avanex, Inc. All rights reserved. CONFIDENTIALITY NOTICE: The information contained in this presentation is Avanex confidential information. Any dissemination, distribution or copying of this presentation or disclosure of the information contained within by any unauthorized person is strictly prohibited. WISDOM PROJECT 12/19/07 PLAN FOR SECOND YEAR WORK TEST PLATFORM HW DESIGN

2. ©2006 Avanex, Inc. All rights reserved. CONFIDENTIALITY NOTICE: The information contained in this presentation is Avanex confidential information. Any dissemination, distribution or copying of this presentation or disclosure of the information contained within by any unauthorized person is strictly prohibited. 2 WISDOM Y02 PLAN  AVANEX planned contribution in WISDOM project Y02 is in WP4: optical processing sub-system development. With a more focus on electrical design and software control  Contribute to finalize architecture of the control electronic requirement By Optimizing the number of block to design By Offering a scalable architecture By defining proper control structure  Finalize the electronic requirement Specify each electrical block to develop Specify each software block to develop  Provide test structure for evaluation and control

3. ©2006 Avanex, Inc. All rights reserved. CONFIDENTIALITY NOTICE: The information contained in this presentation is Avanex confidential information. Any dissemination, distribution or copying of this presentation or disclosure of the information contained within by any unauthorized person is strictly prohibited. 3 Platform Approach  Use of a single PCB platform design to drive different building blocks MZI Switch Optional pattern generator  One PCB can drive 2 independent switch/MZI  Configuration done by HW selection  Settings loaded using configuration files GUI configured by HW PCBA configuration  GUI to configure as well functions (MZI/SW) as HW optics (SOA/Heater)  Use of USB interface to // boards (up to 10) Each board have separated configuration file Use of ECL technology to offer high speed and fast transient circuit – Use of shifted ECL interface to allow 50  direct DC load to GND

4. ©2006 Avanex, Inc. All rights reserved. CONFIDENTIALITY NOTICE: The information contained in this presentation is Avanex confidential information. Any dissemination, distribution or copying of this presentation or disclosure of the information contained within by any unauthorized person is strictly prohibited. 4 SW interface

5. ©2006 Avanex, Inc. All rights reserved. CONFIDENTIALITY NOTICE: The information contained in this presentation is Avanex confidential information. Any dissemination, distribution or copying of this presentation or disclosure of the information contained within by any unauthorized person is strictly prohibited. 5 MZI driver block 1/2 DAC ADC Heater Current Set Or Heater Voltage set HeaterCurrentSense HEATER DRIV ER HeaterVoltageSense Heater Enable/Disable status µC DAC ADC SOACurrentSetSOACurrentSet SOACurrentSe nse SOA DRIV ER SOAVoltageSe nse SOA Enable/Disable status

6. ©2006 Avanex, Inc. All rights reserved. CONFIDENTIALITY NOTICE: The information contained in this presentation is Avanex confidential information. Any dissemination, distribution or copying of this presentation or disclosure of the information contained within by any unauthorized person is strictly prohibited. 6 MZI driver block 2/2 µC DRIV ER DAC ADC Pe lti er Cu rr en tS et PeltierCurrentSense Peltier Rth Analog_Peltier _ TempSens e PeltierVoltageSense T e m p er at ur e _ S et PID Digital_Peltier _ TempSens e TEC Enable/Disable status

7. ©2006 Avanex, Inc. All rights reserved. CONFIDENTIALITY NOTICE: The information contained in this presentation is Avanex confidential information. Any dissemination, distribution or copying of this presentation or disclosure of the information contained within by any unauthorized person is strictly prohibited. 7 Switch Block µC DAC ADC SOACurrentSetSOACurrentSet SOACurrentSe ns e SOA DRIV ER SOAVoltageSe nse SOA Enable/Disable status Re sist or 50 Oh ms RF ECL input shifted, DC coupled µC DRI VER DAC ADC P el ti e r C u rr e n t S et PeltierCurrentSense Peltier Rth Analog_Peltier _ TempS ense PeltierVoltageSense Temperature_SetTemperature_Set PID Digital_Peltier _ TempS ense TEC Enable/Disable status

8. ©2006 Avanex, Inc. All rights reserved. CONFIDENTIALITY NOTICE: The information contained in this presentation is Avanex confidential information. Any dissemination, distribution or copying of this presentation or disclosure of the information contained within by any unauthorized person is strictly prohibited. 8 Pattern generator block Target pattern DC coupled < 200 MHZ 8 /16/ 32 bits circular registers & electronic control Pattern triger < 200 MHZ µC Delayed initialising pulse DC coulped < 200 MHZ Driver Electronic system control EC L OU TP UT TE CH NO LO GY SH IF TE D Target bit rate AC couoled ; Vpp = 500 mv Load target N bits Delayed Reset pulse DC coulped < 200 MHZ Delayed Output gate DC coulped < 200 MHZ Delayed Input data select control DC coulped < 200 MHZ