1. J. Ye SMU Joint ATLAS-CMS Opto-electronics working group, April 10-11, 2008 CERN 1 Test Results on LOC1 and Design considerations for LOC2 LOC1 test results: LOC1 test results: Electric output: rise/fall times, amplitude. Electric output: rise/fall times, amplitude. Eye diagram. Eye diagram. Understand the jitter. Understand the jitter. Bit error rate. Bit error rate. LOC2 design. LOC2 design.

2. J.Ye, SMU 2 Joint ATLAS-CMS Opto-electronics working group, April 10-11, 2008 CERN LOC1 block diagram Five function blocks: the input 8B/10B encoder, the 20:1 serializer, the output driver, the PLL and clock unit, and the control and configuration. Five function blocks: the input 8B/10B encoder, the 20:1 serializer, the output driver, the PLL and clock unit, and the control and configuration. Solid line box: implemented; dashed line box: not implemented. Solid line box: implemented; dashed line box: not implemented. Loc1 is the 1 st prototype only good for tests in lab. Loc1 is the 1 st prototype only good for tests in lab. PLL + clock unit 5:1 DFF based serializer 2:1 mux 5:1 DFF based serializer 2:1 mux 8B/10B encoder 16 bit data 2:1 mux Output driver Ref. clk Current driver to VCSEL CML driver to VCSEL CML signal Control + configuration

3. J.Ye, SMU 3 Joint ATLAS-CMS Opto-electronics working group, April 10-11, 2008 CERN LOC1 basic electrical characteristics Input power supply: Input power supply: 2.5V (Analog/Digital), 3.3V VCSEL 2.5V (Analog/Digital), 3.3V VCSEL Power consumption (with current configuration) ~200mW. Power consumption (with current configuration) ~200mW. Input data signals Input data signals LVCMOS 2.5V LVCMOS 2.5V Reference clock 62.5MHz 20bit 8B/10B encoded input data

4. J.Ye, SMU 4 Joint ATLAS-CMS Opto-electronics working group, April 10-11, 2008 CERN LOC1 test system diagram ElectricalDifferential Data Clock LVDS Driver Board LVDS Receiver Board Clock distribution I/O to PC FPGA: PRBS generator 8B/10B encoder Error detection LVDS Interface Board LOC1 Carrier Board TLK Carrier Board FPGA Board TLK Interface Board Test point Tektronix 20GHz real-time oscilloscope (DSA72004) and Anritsu BERT were used for the tests. The VCSEL driver is not functioning. All tests were carried out through the CML driver on electrical signals only. Signal amplitude, rise/fall times measurement and jitter analysis were performed at the test point (see figure). BER was measured with the Anritsu BERT. Data Clock

5. J.Ye, SMU 5 Joint ATLAS-CMS Opto-electronics working group, April 10-11, 2008 CERN Rise/Fall time and Amplitude The logic in the digital part, and the PLL + clock unit are functioning as designed. The output serial bits are correct, checked on the scope. The differential signal amplitude is about 240mV, measured by a differential probe. This is much lower than the 400 mV design spec. The reason of this problem is known and will be fixed in LOC2. Rise/Fall times are data pattern dependent, measured to be around 150ps. This is boarder line for 2.5 Gbps signal. The reason is not known. The whole driver design will be abandoned. We will use a new driver design in LOC2. Comma (k28.5) code on differential electrical channel

6. J.Ye, SMU 6 Joint ATLAS-CMS Opto-electronics working group, April 10-11, 2008 CERN Eye diagram Eye diagram of the Input 2 7 -1 Pseudo random data. UI = 400ps, for 2.5 Gbps. An eye diagram is measured. There is huge jitter generated inside the chip. Careful measurements were carried out to identify the components as well as possible sources of this jitter. We think that we understand this problem very thoroughly. The huge DJ comes from the 4-arm 2-stage mux serializer design. This architecture is not necessary. New serializer design will be implemented in LOC2 to address this problem. The RJ comes mostly from the PLL. Efforts are spent to improve the PLL design for LOC2.

7. J.Ye, SMU 7 Joint ATLAS-CMS Opto-electronics working group, April 10-11, 2008 CERN Jitter measurement method DSA72004 employs software package TDSJIT3 for jitter analysis. DSA72004 employs software package TDSJIT3 for jitter analysis. Sample records at 40ps and up to 50M data points in one data file — a snapshot of 2ms waveform length, for long term jitter analysis. Sample records at 40ps and up to 50M data points in one data file — a snapshot of 2ms waveform length, for long term jitter analysis. Algorithm performed in the frequency domain. Algorithm performed in the frequency domain. RJ and DJ components are extracted. RJ and DJ components are extracted.

8. J.Ye, SMU 8 Joint ATLAS-CMS Opto-electronics working group, April 10-11, 2008 CERN Jitter measurement with TDSJIT3 Jitter spectrum Results: RJ_rms = 10ps, DJ_pk-pk = 230ps. Out of 230 DJ, the periodic jitter coming from the serializer structure is175ps. This can be eliminated in LOC2. Total jitter (@10 -12 BER) = 310ps. Reminder: UI = 400ps.

9. J.Ye, SMU 9 Joint ATLAS-CMS Opto-electronics working group, April 10-11, 2008 CERN Periodic jitter A large periodic jitter is observed. This strong data dependent, n×492KHz jitter structure (2.5GHz/127/40 = 492KHz) is a clear indication that the jitter comes from an unmatched 4-arm 2-stage serializer. New serializer structure will be implemented in LOC2 to address this problem.

10. J.Ye, SMU 10 Joint ATLAS-CMS Opto-electronics working group, April 10-11, 2008 CERN Bit error rate measurement BERT signal generator 62.5MHz FPGA board LOC1 BERT Error Detect 62.5MHz20bit Data Serialized Data 2.5GHz BER The BER measurement system We use Anritsu MP1763/1764 BER Tester for this test The input amplitude is 110mV because of the Differential to single-ended converter.

11. J.Ye, SMU 11 Joint ATLAS-CMS Opto-electronics working group, April 10-11, 2008 CERN The bathtub curve The bathtub curve at 2.5Gbps, the best BER reached is ~10 -11. By shifting the reference clock with respect the parallel data, we get the bathtub curve. From this curve we extract: DJ_pk-pk = 235ps, RJ_rms =18ps, and total jitter = 478ps (@10 -12 BER) The low signal amplitude might cause the large RJ measurement. The BERT error detect requires 250 mV amplitude input, but our input is 240mV/2 ~ 110mV.

12. J.Ye, SMU 12 Joint ATLAS-CMS Opto-electronics working group, April 10-11, 2008 CERN LOC2 block diagram The preliminary LOC2 block diagram We aim LOC2 for a usable chip for “users” to implement in their systems. A design document is being drafted and circulated for experts’ opinions. A design document review with people from ATLAS LAr and ID (users + designers) will be held in ~2-3 weeks time frame. A design review will be held end of 2008. We aim for a submission in early 2009, and make the chip available mid-2009. 16 bit Input register LVDS to LVCMOS 2:1 MUX to 8 bit 8B/10B Comma 2 7 -1 PRBS PLL + clks MUX Cntrl config Odd bits shift register Even bits shift register Latch CML driver 2:1 MUX Data Clk_ref Cntrl/Config 16 LVDS 10 bit Serial output to Versatile Link

13. J.Ye, SMU 13 Joint ATLAS-CMS Opto-electronics working group, April 10-11, 2008 CERN LOC2 key features A Serializer at 3.125Gbps or higher speeds; A Serializer at 3.125Gbps or higher speeds; Differential electrical output (CML), to be coupled to the Versatile Link input; Differential electrical output (CML), to be coupled to the Versatile Link input; Compatible with commercial GBE receivers (8B/10B encoder); Compatible with commercial GBE receivers (8B/10B encoder); 16 bit LVDS differential data input; 16 bit LVDS differential data input; Differential 156 MHz reference clock; Differential 156 MHz reference clock; Data sampling at rising or falling edge of the reference clock Data sampling at rising or falling edge of the reference clock Internal 2 7 -1 PRBS; Internal 2 7 -1 PRBS; Single 2.5 voltage power supply. Single 2.5 voltage power supply.

14. J.Ye, SMU 14 Joint ATLAS-CMS Opto-electronics working group, April 10-11, 2008 CERN Conclusion LOC1 is under tests at SMU. The testing results provide a lot of information for LOC2 design. LOC1 is under tests at SMU. The testing results provide a lot of information for LOC2 design. Irradiation tests on LOC1 will be carried out June/July 2008. Irradiation tests on LOC1 will be carried out June/July 2008. The design on LOC2 started. A design document is being generated and a design review will be held April 2008 in the community. The design on LOC2 started. A design document is being generated and a design review will be held April 2008 in the community. We aim for a submission early 2009 and having chips mid-2009. We aim for a submission early 2009 and having chips mid-2009.