Embedded Systems Design with Qsys and Altera Monitor Program Tutorial #2

Material for teaching embedded systems Tutorials on Altera’s embedded processors Nios II ARM Cortex A9 Lab exercises that use these processors Set context for talking about the ARM processor. Want to teach you how to use the DE1-SoC which has the ARM processor on it. This course we will focus on the ARM processor.

ARM Cortex A9 Processor + programmable FPGA Cyclone V SoC ARM Cortex A9 Processor + programmable FPGA Cyclone V SoC ARM Hard Processor System FPGA

Altera HPS Block Diagram ARM

Altera HPS Block Diagram 4 GB HPS ARM 3 GB L2 Cache 2 GB 1 GB 0 GB

Altera HPS Block Diagram 4 GB HPS ARM 3 GB L2 Cache L3 Interconnect 2 GB 1 GB 0 GB

Altera HPS Block Diagram 4 GB HPS ARM 3 GB Boot ROM L2 Cache 2 GB 1 GB Boot Region 0 GB

Altera HPS Block Diagram 4 GB HPS ARM 3 GB SDRAM Window Boot ROM L2 Cache 2 GB SDRAM Controller 1 GB DDR3 Chips Boot Region 0 GB

Altera HPS Block Diagram 4 GB HPS ARM 3 GB SDRAM Window Boot ROM L2 Cache 2 GB SDRAM Controller Previously we ran starting at addr 0 that’s because AMP automatically extended the SDRAM window all the way down to 0 1 GB DDR3 Chips Boot Region 0 GB

Altera HPS Block Diagram 4 GB HPS ARM 3 GB SDRAM Window On-Chip RAM Boot ROM L2 Cache 2 GB SDRAM Controller Bunch of peripherals like onchip memory 1 GB DDR3 Chips Boot Region 0 GB

Altera HPS Block Diagram 4 GB HPS ARM Timers 3 GB SDRAM Window On-Chip RAM Boot ROM L2 Cache 2 GB SDRAM Controller 1 GB DDR3 Chips Boot Region 0 GB

Altera HPS Block Diagram 4 GB HPS ARM Timers 3 GB SDRAM Window On-Chip RAM Boot ROM L2 Cache 2 GB GPIO SDRAM Controller 1 GB LEDG KEY DDR3 Chips Boot Region 0 GB

Altera HPS Block Diagram 4 GB HPS ARM Timers 3 GB SDRAM Window On-Chip RAM Boot ROM L2 Cache 2 GB Ports GPIO SDRAM Controller 1 GB USB Ethernet LEDG KEY DDR3 Chips Boot Region 0 GB

Altera HPS Block Diagram 4 GB HPS Peripherals ARM Timers 3 GB SDRAM Window On-Chip RAM Boot ROM L2 Cache 2 GB Ports GPIO SDRAM Controller 1 GB USB Ethernet LEDG KEY DDR3 Chips Boot Region 0 GB

How About Communication with the FPGA? 4 GB HPS FPGA Peripherals ARM Timers 3 GB SDRAM Window On-Chip RAM Boot ROM L2 Cache 2 GB Ports GPIO SDRAM Controller 1 GB USB Ethernet LEDG KEY DDR3 Chips Boot Region 0 GB

There are Several Bridges Between the HPS and FPGA 4 GB HPS FPGA Peripherals ARM Timers 3 GB SDRAM Window On-Chip RAM Boot ROM L2 Cache Bridges 2 GB Ports GPIO SDRAM Controller 1 GB USB Ethernet LEDG KEY DDR3 Chips Boot Region 0 GB

HPS-to-FPGA Bridge 4 GB HPS FPGA Peripherals ARM FPGA Slave Region Timers 3 GB SDRAM Window On-Chip RAM Boot ROM On-Chip Cores L2 Cache H2F 2 GB Ports GPIO SDRAM Controller Ports This bridge will lalow you to connect any peripheral in FPGA to ARM processor. Addr range is shown in the light blue. 1 GB USB Ethernet LEDG KEY DDR3 Chips LEDR Switches Etc. Boot Region 0 GB

Lightweight HPS-to-FPGA Bridge 4 GB HPS FPGA Peripherals ARM FPGA Slave Region Timers 3 GB SDRAM Window On-Chip RAM Boot ROM On-Chip Cores L2 Cache LW H2F 2 GB Ports GPIO SDRAM Controller Ports Much smaller addr range, within peripherals region. HPS bridge is large bridge with low latency for bulk transfers. LW bridge is usually used to communicate with control registers, and communication thru this bridge will not interrupt bulk transfers on the bigger HPS bridge. 1 GB USB Ethernet LEDG KEY DDR3 Chips LEDR Switches Etc. Boot Region 0 GB

Use Qsys and Quartus to Create the FPGA Portion 1 4 GB HPS FPGA Peripherals ARM FPGA Slave Region Timers 3 GB SDRAM Window On-Chip RAM Boot ROM On-Chip Cores L2 Cache LW H2F 2 GB Ports GPIO SDRAM Controller Ports Much smaller addr range, within peripherals region. HPS bridge is large bridge with low latency for bulk transfers. LW bridge is usually used to communicate with control registers, and communication thru this bridge will not interrupt bulk transfers on the bigger HPS bridge. 1 GB USB Ethernet LEDG KEY DDR3 Chips LEDR Switches Etc. Boot Region 0 GB

Quartus System Integration Tool (Qsys) Tool for connecting components to create a system. Use prebuilt componenets, but can create your own as well. Qsys will generate all of the interconnect fabric for you.

Qsys Windows Selected Components And connectivity Available Components Available components listed in the library window. Your own components that you’ve added will be in list as well. Main system subwindow that shows selected components and their connectivity. Messages window to show info messages… Available Components Messages

Select Components to add to the System

Configure the Components using their Wizards

HPS Component: Adding/Removing FPGA to SDRAM Bridges

HPS Component: Editing HPS Peripherals

HPS Component: Editing SDRAM Parameters

Component is now in the System

Creating a System in Qsys General Steps Select a processor Altera HPS or a Nios Add off-the-shelf with standard interfaces (SPI, I2C, JTAG, etc.) to help solve the problem Use existing drivers or write one yourself Sometimes an existing driver needs to be augmented for a particular application Add custom components when the needed ones are not available (or too expensive) Add I/O as needed Write code to run on the system Usually a single program

How to put them together? Qsys system integration tool Add components Generate the System HDL Quartus II software Synthesize HDL for the FPGA Altera Monitor Program Compile and debug software

Exercise 4: Making a Custom System Use Qsys to make a system with: Altera HPS component PIO cores for: Red LEDs Seven Segments Displays Slider switches Compile the system using the Quartus II software

Step 1: Open the DE1_SoC Project in Quartus II

Step 2: Open the DE1_SoC Project in Quartus II

Step 3: Launch Qsys

Step 4: Select the Computer System

Step 5: The Pre-Started System

Step 6: Add PIO Component for the LEDRs

Step 7: Configure the PIO for the LEDRs

Step 8: Add and Configure a PIO for the 7-Segs

Step 9: Add and Configure a PIO for the Switches

Step 10: Current System

Step 11: Export PIOs’ External Connections Connect the external ports by exporting the external_connection port of the components.

Step 12: Minimize the PIOs

Step 13: Make Connections

Step 14: Go to Address Map Tab Have been mapped to the same address range within the lw bridge…

Step 15: Set the Slave Addresses These are the OFFSETS into the lw bridge. These will result in these registers being placed at the same addresses as the previous example.

Step 16: Generate the System Now we can see that the errors and warnings are gone. We can generate the system!

Step 17: Generate the System Bunch of options.. we]’ll use the default settings.

Step 18: System Generation Finished

Step 18: Generated System module Computer_System ( clk_clk, reset_reset_n, // LEDs ledr_export, // Seven Segs hex3_hex0_export, // Slider Switches sw_export, ... ); FPGA LEDs HPS 7-Segs Switches

Step 19: Create Top Level File for project System must be instantiated in your design Must connect system ports to the I/O ports In this demo the top level file has been created for you Compile your project. Open the DE1_SoC.v to examine the system connectivity while Quartus II compiles the project.

Step 20: Compile the System in Quartus II

Step 21: Wait for Compilation to Finish

What Exactly Did We Just Build? Two files: .sopcinfo file (qsys) .sof file (quartus) HPS FPGA ARM … … … pio_2 . LW H2F … … … pio_1 pio_0 Much smaller addr range, within peripherals region. HPS bridge is large bridge with low latency for bulk transfers. LW bridge is usually used to communicate with control registers, and communication thru this bridge will not interrupt bulk transfers on the bigger HPS bridge.

Please read the instructions at Hands-On Session Please read the instructions at “/exercise4/instructions.pdf” Use provided Quartus project “DE1_SoC.qpf” Use pre-started Qsys system “”Computer_System.qsys” We will be walking around to help with any issues

Exercise 5: Developing an Embedded Application Write a software application to run on the system that we built in the previous exercise Compile the code using Altera Monitor Program Run the program and examine some debugging features of the Altera Monitor Program

Application Code (/exercise5/fpga_gpio.c) Read switches and display on LEDs and 7-Segs int main(void)( volatile int * LEDs = (int *) 0xFF200000; volatile int * HEX3_HEX0 = (int *) 0xFF200020; volatile int * SW_switch = (int *) 0xFF200040; int hex_conversions[16] = {0x3F, ..., 0x71}; while(1) { int value = *SW_switch; *LEDs = value; int first_digit = value & 0xF; int second_digit = (value >> 4) & 0xF; int third_digit = (value >> 8) & 0xF; int hex_value = hex_conversions[first_digit]; hex_value |= hex_conversions[second_digit] << 8; hex_value |= hex_conversions[third_digit] << 16; *HEX3_HEX0 = hex_value; }

Application Code (/exercise5/fpga_gpio.c) Read switches and display on LEDs and 7-Segs int main(void)( volatile int * LEDs = (int *) 0xFF200000; volatile int * HEX3_HEX0 = (int *) 0xFF200020; volatile int * SW_switch = (int *) 0xFF200040; int hex_conversions[16] = {0x3F, ..., 0x71}; while(1) { int value = *SW_switch; *LEDs = value; int first_digit = value & 0xF; int second_digit = (value >> 4) & 0xF; int third_digit = (value >> 8) & 0xF; int hex_value = hex_conversions[first_digit]; hex_value |= hex_conversions[second_digit] << 8; hex_value |= hex_conversions[third_digit] << 16; *HEX3_HEX0 = hex_value; }

Application Code (/exercise5/fpga_gpio.c) Read switches and display on LEDs and 7-Segs int main(void)( volatile int * LEDs = (int *) 0xFF200000; volatile int * HEX3_HEX0 = (int *) 0xFF200020; volatile int * SW_switch = (int *) 0xFF200040; int hex_conversions[16] = {0x3F, ..., 0x71}; while(1) { int value = *SW_switch; *LEDs = value; int first_digit = value & 0xF; int second_digit = (value >> 4) & 0xF; int third_digit = (value >> 8) & 0xF; int hex_value = hex_conversions[first_digit]; hex_value |= hex_conversions[second_digit] << 8; hex_value |= hex_conversions[third_digit] << 16; *HEX3_HEX0 = hex_value; }

Program Behaviour

Program Behaviour

Step 1: Start Altera Monitor Program

Step 2: Create a New Project Sets up the Altera Monitor Program Select files to work with Specify target system

Step 2.1: Specify name, directory and architecture

Step 2.2: Select a Custom System

Step 2.3: Select Program Type

Step 2.4: Add Source File

Step 2.5: Set Board Connection and Select Processor

Step 2.6: Leave Default Memory Settings

Step 3: Program the FPGA with the Custom System

Step 4: Compile and Load Compile your C language program Load the compiled code into the memory on the DE1-SoC board

Step 5: Examine the Window Contents

Step 5: Examine the Window Contents Disassembly

Step 5: Examine the Window Contents Registers

Step 5: Examine the Window Contents Info & Error Msgs

Step 5: Examine the Window Contents Terminal

Step 6: Run the Program and Toggle Switches on Board

Step 7: Pause the Processor

Step 8: Go to 0xff200000 in Memory Window 3 2 1

Step 9: Read PIO Registers (Right Click)

Step 9: Examine Values

Step 10: Alter the Red LED PIO Register (Double Click)

Step 11: Test Other Features Single Step

Step 11: Test Other Features Breakpoints

Step 11: Test Other Features Restart Program

Step 12: Disconnect

Please read the instructions at Hands-On Session Please read the instructions at “/exercise5/instructions.pdf” If you did not finish exercise 4, use the solutions in /exercise5/exercise4_solutions/ We will be walking around to help with any issues

Where did we go from here? Summary of Tutorial #2 Learned how to Use Qsys to build a system Compile a Qsys system in Quartus Write and compile applications for an ARM-based embedded system using Altera Monitor Program Where did we go from here? Tutorials: Introduction to the Altera Qsys System Integration Tool Making Qsys Components Altera Monitor Program Tutorial for ARM Embedded systems laboratory exercises http://university.altera.com Heres what we learned, let me talk about materials you can use for your students