1. Getting Started with Programmable Logic
Class 4: A Simple Design from Start to Finish
3/13/2014
Warren Miller

2. This Week’s Agenda
3/10/14 An Intro to Designing with Prog Logic 3/11/14 Programmable Logic Design Flow 3/12/14 Lattice LCMXO2 Evaluation Board 3/13/14 A Simple Design from Start to Finish 3/14/14 Your Own Design

3. Course Description
Programmable Logic and FPGAs in particular are used in just about every digital electronics system
Getting started on your first FPGA design can be a daunting prospect however
New concepts, new tools, new languages, etc.
This course will provide a painless introduction and a hands on opportunity for you to do your first actual design, making it easy for you to get started on your first programmable logic design

4. Today’s Topics Goals and Objectives Quickly Review Target Hardware
Evaluation Board
LCMXO2 device
Example Design
Review the design in some detail
Go thru the tool flow- step by step
How you do it (and why!)

5. Todays Goals and Objectives
Understand the steps needed to do a design from start to finish
Build confidence in doing your own design
Create a deeper understanding of how the tools, device, example design, IP blocks, reference designs and the evaluation board all work together

6. Evaluation Board MachXO2 1200ZE 4-character 7-segment LCD Display
4 Cap Sense buttons
1Mbit SPI Flash
I2C Temp sensor
Expansion Headers- JTAG, SPI, I2C
Power measurement

7. LCMXO FPGA
PFU Blocks, Embedded RAM, Embedded Blocks, User Flash memory, PLLs, Configuration memory, and Ios
Memory Blocks (8Kx1 to 1Kx9)
Single
Pseudo Dual
True Dual
FIFO
IOs
Resisters, DDR
Delays, Grearbox

8. LCMXO2-1200 FPGA PFU Blocks and Slices Carry, Memory, etc.
For Slices 0 and 1, memory control signals are generated from Slice 2 as follows:
• WCK is CLK
• WRE is from LSR • DI[3:2] for Slice 1 and DI[1:0] for Slice 0 data from Slice 2
• WAD [A:D] is a 4-bit address from slice 2 LUT input

9. Embedded Function Blocks
I2C (2)
SPI (1)
Timer Counter
Wishbone I/F
User Flash Memory
Up to 256Kbits
Page Write
128-bits/Page

10. Demo Design Block Diagram Application: Measure Power SPI/I2C Slave ADC
Push-button
LCD Driver

11. Design Steps Create Project Write Code, RunIP Express
Functional Simulation
Synthesize Design
Translate and Map
Place and Route
Generate Bitstream
Program
Debug

12. Diamond Start Page
Create Project
Follow Progress
Context Views
Tools

13. Write Code and Run IPExpress
Write Code (Design & Testbench)
Run IPExpress
Power Control, SPI, I2C

14. Example Design Docs, I2C_SPI_master, power_control Check HDL
HW, SW, Source, User, Config
Check HDL
Best Known Methods (BKM) are design guidelines that HDL Diagram
uses to analyze your design. BKM checks include the following:
 Connectivity – Checks the pin connectivity of instances throughout the
design.
 Synthesis – Checks for violations of the Sunburst Design coding
styles, as well as other potential synthesis problems.
 Structural Fan-Out – Checks for maximum structural fan-out
violations.
 Coding Styles – Colors modules based on their line count, colors pins
and ports based on their width, validates module names, and also
performs big-endian or little-endian checks on all ports.
 Verification – Validates the existence and timestamps of VCD files. A
series of Lint-like RTL rule checks are run. Modules that have rule
violations are color coded in the HDL Diagram view.

15. Functional Simulation
Active HDL (or ModelSim)
Check files
Run Wizard
Settings
RTL as Stage
Run Simulator
Add Top-Level
Run Simulation
Observe Output

16. Synthesis Lattice Synthesis Engine For MachXO2 Synplify Pro
For other devices
Define Strategy
Run
View Results
Device
Floorplan
Resources

17. Reports View Automatically Displayed Project Summary Process Reports
As Processes complete
Project Summary
Module
Device
Speed Grade
Package
Process Reports
Map
Place and Route
I/O Timing

18. Implement Design Translate, Map, Place, Route, and/or Bitstream
Click on the Process Icons
Define Settings
Pins
Timing
View Reports

19. Timing
Source
Destination
Slack
Arrival
Required
Levels
Clock Skew

20. Download and Debug Create Bit file Download Bit file via Programmer
Reveal Debugger

21. Download and Debug Create Bit file Download Bit file via Programmer
Reveal Debugger

22. Run Demo Design Observe results on LCD See results on terminal
What power results do you get in the two cases?
Are there simple changes you would like to make to the design?
Change initial display settings?
Auto-range the current display?
Use button as a timer start?

23. Additional Resources
Lattice Diamond Tutorials Lattice Diamond Videos Users Handbook Lattice Diamond Web Page Diamond User Guide

24. This Week’s Agenda
3/10/14 An Intro to Designing with Prog Logic 3/11/14 Programmable Logic Design Flow 3/12/14 Lattice LCMXO2 Evaluation Board 3/13/14 A Simple Design from Start to Finish 3/14/14 Your Own Design