CS151 Introduction to Digital Design Chapter 3: Combinational Logic Design 3-5 Combinational Functional Blocks 3-6 Rudimentary Logic Functions 3-7 Decoding 1Created by: Ms.Amany AlSaleh

2 Overview  Part 2 – Combinational Logic Functions and functional blocks Rudimentary logic functions Decoding using Decoders Implementing Combinational Functions with Decoders Encoding using Encoders Selecting using Multiplexers Implementing Combinational Functions with Multiplexers Created by: Ms.Amany AlSaleh

3 3-5 Combinational Functional Blocks  The functions considered are those found to be very useful in design.  Corresponding to each of the functions is a combinational circuit implementation called a functional block.  In the past, functional blocks were packaged as small- scale-integrated (SSI), medium-scale integrated (MSI), and large-scale-integrated (LSI) circuits.  Today, they are often simply implemented within a very- large-scale-integrated (VLSI) circuit. Created by: Ms.Amany AlSaleh

4 3-6 Rudimentary Logic Functions  Most elementary combinational logic functions: Value fixing Transferring Inverting Enabling Use only variables and constants Do not involve Boolean operators Involves only one logic gate per variable. Involves one or two logic gates per variable. Created by: Ms.Amany AlSaleh

5 3-6 Rudimentary Logic Functions (Cont.)  Value fixing, Transferring and Inverting Functions of a single variable X. Transferring Inverting Value Fixing Transferring Inverting Value Fixing Created by: Ms.Amany AlSaleh

6 3-6 Rudimentary Logic Functions (Cont.) Multiple-Bit Rudimentary Functions:  Suppose we have four functions: F3, F2, F1, and F0 that make up a 4-bit function F.  This multiple-bit function can be referred to as F(3:0) or simply F.  F3  msb & F0  lsb then F = (F3, F2, F1, F0)  E.g. if F3= 0, F2= 1, F1= A, and F0= A’ then F is defined as (0, 1, A, A’) For A= 0  F= (0, 1, 0, 1) 0 F 3 1 F 2 F 1 A F 0 A Created by: Ms.Amany AlSaleh

7 3-6 Rudimentary Logic Functions (Cont.) Multiple-Bit Rudimentary Functions (Cont.)  A wide line is used to represent a bus which is a vector signal  In (b) of the example, F = (F 3, F 2, F 1, F 0 ) is a bus.  The bus can be split into individual bits as shown in (b)  Sets of bits can be split from the bus as shown in (c) for bits 2 and 1 of F.  The sets of bits need not be continuous as shown in (d) for bits 3, 1, and 0 of F.  See Example 3-8 on page 117 in your text book. (d) (a)(b) 4 2:1 F(2:1) 2 F (c) F 4 3,1:0 F(3), F(1:0) 3 0 F 3 1 F 2 F 1 A F 0 A 0 1 A F 0 A Created by: Ms.Amany AlSaleh

8 Enabling Function  Enabling permits an input signal to pass through to an output.  Disabling blocks an input signal from passing through to an output, replacing it with a fixed value.  The value on the output when it is disable can be Hi-Z (as for three- state buffers and transmission gates), 0, or 1.  When disabled, 0 output  When disabled, 1 output EN= 0  Output fixed at 0 EN= 0  Output fixed at 1 Created by: Ms.Amany AlSaleh

9 Enabling Function Example  Car Electrical Control Using Enabling: Ignition Switch IG: 0  Off & 1  On Light Switch LS: 0  Off & 1  On Radio Switch RS: 0  Off & 1  On Window Switch WS: 0  Off & 1  On Lights L: 0  Off & 1  On Radio R: 0  Off & 1  On Power Windows W: 0  Off & 1  On Created by: Ms.Amany AlSaleh

Decoding (Cont.)  An n-bit binary code is capable of representing up to 2 n distinct elements of coded information.  Decoding is the conversion of an n-bit input code to an m- bit output code with n ≤m ≤ 2 n.  Circuits that perform decoding are called decoders.  A decoder is a combinational circuit that converts binary information from n input lines to 2 n unique output lines. n-to-m Line Decoder n inputs m outputs m <= 2 n Created by: Ms.Amany AlSaleh

Decoding (Cont.)  Functional blocks for decoding are called n-to-m line decoders, where m ≤ 2 n, and generate 2 n (or fewer) minterms for the n input variables  decoder may have unused bit combinations on its input for which no corresponding m-bit code appears at the output.  Applications: Microprocessor memory system: selecting different banks of memory. Microprocessor I/O: Selecting different devices. Microprocessor instruction decoding: Enabling different functional units. Memory: Decoding memory addresses (e.g. in ROM). Created by: Ms.Amany AlSaleh

12 Decoder Example 1  1-to-2-Line Decoder: n=1  m= 2 If A=0  D 0 = 1 and D 1 = 0 If A=1  D 0 = 0 and D 1 = 1 D0= A’ D1= A Created by: Ms.Amany AlSaleh

13 Decoder Example 2  2-to-4-Line Decoder: n=2  m= 4  Notice they are minterms.  Note that the 2-4-line made up of:  2 1-to-2- line decoders  4 AND gates. Number of AND gates: 4 Created by: Ms.Amany AlSaleh

14 Decoder Example 3  3-to-8-Line Decoder: example: Binary-to-octal conversion. n=3  m= 8  Notice they are minterms Created by: Ms.Amany AlSaleh

15 Decoder Example 3  3-to-8-Line Decoder (Cont.): n=3  m= 8 m0 m1 m2 m3 m4 m5 m6 m7 Note: the 3-8-line made up of:  2-to-4-line decoder  1-to-2-line decoder  8 AND gates Number of AND gates= 8 Created by: Ms.Amany AlSaleh

16 Decoder with Enable  In general, attach m-enabling circuits to the outputs  The decoder is disabled when E = 1  all outputs are 0.  The decoder is enabled when E = 1. The output whose value is 1 represents the minterm is selected by inputs A 0 and A 1.  A Decoder with enable input is called a decoder/demultiplexer.  See truth table below for the function: Note use of X’s to denote both 0 and 1 Combination containing two X’s represent four binary combinations Created by: Ms.Amany AlSaleh

17 Decoder Expansion - Example 1 Enable Used for Expansion  Decoders with enable inputs can be connected together to form a larger decoder circuit. Enable Created by: Ms.Amany AlSaleh

18 Decoder Expansion - Example 2  Construct a 5-to-32-line decoder using four 3-8-line decoders with enable inputs and a 2-to-4-line decoder. D 0 – D 7 D 8 – D 15 D 16 – D 23 D 24 – D 31 A3A4A3A4 A0A1A2A0A1A2 2-4-line Decoder 3-8-line Decoder E E E E Created by: Ms.Amany AlSaleh

19 Decoders Can Implement Any Function!  Since any function can be represented as a some-of-minterms, a decoder can be used to generate the minterms, and an external OR gate to form their sum.  A combinational circuit with n inputs and m outputs can be implemented with an n-to-2 n line decoder and m OR gates. S(X,Y,Z)=  m (1,2,4,7) C(X,Y,Z)=  m (3,5,6,7) Number of Ones = 3 Number of Ones = 0 Number of Ones = 1 Number of Ones = 2 X Y ZCS Created by: Ms.Amany AlSaleh

20 F1 Decoders Can Implement Any Function!  F1 = A' B C' D + A' B' C D + A B C D AB 0A'B'C'D' 1A'B'C'D 2A'B'CD' 3A'B'CD 4A'BC'D' 5A'BC'D 6A'BCD' 7A'BCD 8AB'C'D' 9AB'C'D 10AB'CD' 11AB'CD 12ABC'D' 13ABC'D 14ABCD' 15ABCD 4:16 DEC Enable CD Created by: Ms.Amany AlSaleh