1. ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Lecture 7 Dr. Shi Dept. of Electrical and Computer Engineering

2. BINARY ADDERS

3. Overview  Addition of binary data is fundamental  Need to determine hardware implementation  Represent inputs and outputs  Inputs: single bit values, carry in  Outputs: Sum, Carry  Hardware features  Create a single-bit adder and chain together  Dealing with overflow  What happens if numbers are too big?

4. 4-Bit Adder Think top-down: How to break a problem into pieces?

5. Multiple-bit Addition A 3 A 2 A 1 A 0 0 1 A 0 1 1 1 B 3 B 2 B 1 B 0 B 0 1 0 1 1 1 A B 0 1 0 1 1 1 1 A i +B i C i SiSi C i+1 Consider single-bit adder for each bit position. Each bit position creates a sum and carry

6. Full Adder Block Diagram Single-bit full adder, building block of large adders Common piece of computer hardware

7. Full Adder 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 11 11 CiCi AiBiAiBi 00011110 0 1 SiSi Full adder includes carry in C i Notice interesting pattern in Karnaugh map.

8. Full Adder 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 1 111 CiCi AiBiAiBi 00011110 0 1 C i+1 Now consider implementation of carry out Two outputs per full adder bit (C i+1, S i ) Note: 3 inputs

9. Full Adder Implementation S i = C i  (A i  B i ) C i+1 = A i · B i + C i · (A i  B i )

10. Full Adder A full adder can be made from two half adders (plus an OR gate). Hardware repetition simplifies hardware design

11. 4-Bit Adder C 1 1 1 0 A 0 1 0 1 B 0 1 1 1 S 1 1 0 0 Chain single-bit adders together. What does this do to delay?

12. Half Adder (not very useful) C AB S 00 01 A 0 B 0 S 0 C 1 0 0 0 1 1 0 1 0 1 1 0 1 Dec Binary 1 1 +1 2 10 Add two binary numbers A 0, B 0 -> single bit inputs S 0 -> single bit sum C 1 -> carry out

13. Multiplexers

14.  Select an input value with one or more select bits  Use for transmitting data  Allows for conditional transfer of data  Sometimes called a mux

15. 4– to– 1- Line Multiplexer

16. Quadruple 2–to–1-Line Multiplexer Notice enable bit Notice select bit 4 bit inputs

17. Multiplexer as combinational modules  Connect input variables to select inputs of multiplexer (n-1 for n variables)  Set data inputs to multiplexer equal to values of function for corresponding assignment of select variables  Using a variable at data inputs reduces the size of the multiplexer

18. Implementing a Four- Input Function with a Multiplexer

19. Multiplexers & Shannon Expansion

20. Shannon Expansion Theorem  The Shannon expansion develops the idea that Boolean functions can be reduced by means of the identity:  where F is any function and F x and F x' are Shannon cofactors of F.

21. Example f = yz + xyz' + x'y'z = yz(x' + x) + xyz' + x'y'z = x'yz + xyz + xyz' + x'y'z = x'(yz + y'z) + x(yz + yz') = x'g x' + xg x

22. Expand about 2 variables

23. Multiplexer Implementation

24. DECODERS

25. Overview  Binary decoders  Converts an n-bit code to a single active output  Can be developed using AND/OR gates  Can be used to implement logic circuits.  Binary encoders  Converts one of 2 n inputs to an n-bit output  Useful for compressing data  Can be developed using AND/OR gates  Both encoders and decoders are extensively used in digital systems

26. Binary Decoder  Black box with n input lines and 2 n output lines  Only one output is a 1 for any given input Binary Decoder n inputs 2 n outputs Enable

27. 2-to-4 Binary Decoder  From truth table, circuit for 2x4 decoder is:  Note: Each output is a 2- variable minterm (X'Y', X'Y, XY' or XY) F 0 = X'Y'E F 1 = X'YE F 2 = XY'E F 3 = XYE XY Truth Table: 2-to-4 Decoder X Y F0 F1 F2 F3 Enable Enable = 1

28. 3-to-8 Binary Decoder F 1 = x'y'zE xzy F 0 = x'y'z’E F 2 = x'yz'E F 3 = x'yzE F 5 = xy'zE F 4 = xy'z'E F 6 = xyz'E F 7 = xyzE Truth Table: 3-to-8 Decoder X Y F0 F1 F2 F3 F4 F5 F6 F7 Z Enable Enable = 1

29. Implementing Functions Using Decoders  Any n-variable logic function can be implemented using a single n-to-2 n decoder to generate the minterms  OR gate forms the sum.  The output lines of the decoder corresponding to the minterms of the function are used as inputs to the or gate.  Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2 n decoder with m OR gates.  Suitable when a circuit has many outputs, and each output function is expressed with few minterms.

30.  Example: Full adder S(x, y, z) =  (1,2,4,7) C(x, y, z) =  (3,5,6,7) 3-to-8 Decoder S2S1S0S2S1S0 x y z 0123456701234567 S C Implementing Functions Using Decoders Enable Enable = 1

31. Use two 3 to 8 decoders to make 4 to 16 decoder  In this example, only one decoder can be active at a time.  x, y, z effectively select output line for w

32. Encoders

33.  If the a decoder's output code has fewer bits than the input code, the device is usually called an encoder. e.g. 2 n -to-n  The simplest encoder is a 2 n -to-n binary encoder  One of 2 n inputs = 1  Output is an n-bit binary number............ 2 n inputs n outputs Binary encoder

34. 8-to-3 Binary Encoder At any one time, only one input line has a value of 1. 00 00000100101 00000010110 00000001111 I0I1I2I3I4I5I6I7I0I1I2I3I4I5I6I7 y 0 = I 1 + I 3 + I 5 + I 7 y 1 = I 2 + I 3 + I 6 + I 7 y 2 = I 4 + I 5 + I 6 + I 7

35. 8-to-3 Priority Encoder What if more than one input line has a value of 1? Ignore “lower priority” inputs. Idle indicates that no input is a 1.

36. Priority Encoder (8 to 3 encoder)  Priority Encoder : H7=I7 (Highest Priority) H6=I6·I7’ H5=I5·I6’ ·I7’ H4=I4·I5’ ·I6’·I7’ H3=I3.I4’·I5’ ·I6’·I7’ H2=I2.I3’·I4’ ·I5’·I6’ ·I7’ H1=I1· I2’ ·I3’·I4’ · I5’·I6’ ·I7’ H0=I0·I1’ ·I2’·I3’ ·I4’ ·I5’ ·I6’ ·I7’ IDLE= I0’ ·I1’ · I2’ ·I3’ ·I4’ ·I5’ ·I6’ ·I7’ I1 I2 I3 I4 I5 I6 I0 I7 H1 H2 H3 H4 H5 H6 H0 H7 IDLE

37. Priority Encoder (8 to 3 encoder)  Assign priorities to the inputs  When more than one input are asserted, the output generates the code of the input with the highest priority  Priority Encoder : H7=I7 (Highest Priority) H6=I6·I7’ H5=I5·I6’ ·I7’ H4=I4·I5’ ·I6’·I7’ H3=I3.I4’·I5’ ·I6’·I7’ H2=I2.I3’·I4’ ·I5’·I6’ ·I7’ H1=I1· I2’ ·I3’·I4’ · I5’·I6’ ·I7’ H0=I0·I1’ ·I2’·I3’ ·I4’ ·I5’ ·I6’ ·I7’ IDLE= I0’ ·I1’ · I2’ ·I3’ ·I4’ ·I5’ ·I6’ ·I7’  Encoder Y0 = I1 + I3 + I5 + I7 Y1 = I2 + I3 + I6 + I7 Y2 = I4 + I5 + I6 + I7 Y1 Y2 Y0 IDLE I1 I2 I3Y1 Y2I4 I5 I6 I0 Y0 I7 Binary encoder Priority Circuit I1 I2 I3 I4 I5 I6 I0 I7 H1 H2 H3 H4 H5 H6 H0 H7 IDLE I1 I2 I3 I4 I5 I6 I0 I7 Priority encoder