Download presentation

1
**CPEN 315 - Digital System Design**

Spring 2008 Combinational Functions and Circuits Chapter 3 © Logic and Computer Design Fundamentals, 4rd Ed., Mano © 2008 Pearson Prentice Hall

2
**Overview Functions and Functional Blocks Decoding Encoding Selecting**

Implementing Combinational Functions Using: Decoders and OR gates Multiplexers (and inverter) ROMs PLAs PALs

3
**Functions and Functional Blocks**

The functions considered are those found to be very useful in design Corresponding to each of the functions is a combinational circuit implementation called a functional block. In the past, many functional blocks were implemented as SSI, MSI, and LSI circuits. Today, they are often simply parts within VLSI circuits.

4
**Simple Logic Functions**

Functions of a single variable Can be used on the inputs to functional blocks.

5
**Enabling Functions Enabling Permits an input signal to pass**

Disabling Permits an input signal to pass through to an output Blocks an input signal from Passing through to an output Example: The ignition switch = EN Lights = X

6
Decoding Decoding - the conversion of an n-bit input code to an m-bit output code such that each valid code word produces a unique output code Circuits that perform decoding are called decoders Here, functional blocks for decoding are called n-to-m line decoders, and they generate 2n (or fewer) minterms for the n input variables

7
Decoder Examples 1-to-2-Line Decoder 2-to-4-Line Decoder

8
**Decoder with Enable Example**

In general, attach m-enabling circuits to the outputs See truth table below for function Note use of X’s to denote both 0 and 1 Combination containing two X’s represent four binary combinations 2-to-4-Line Decoder with Enable

9
Encoding Encoding - the opposite of decoding - the conversion of an m-bit input code to a n-bit output code such that each valid code word produces a unique output code Circuits that perform encoding are called encoders An encoder has 2n (or fewer) input lines and n output lines which generate the binary code corresponding to the input values Typically, an encoder converts a code containing exactly one bit that is 1 to a binary code corres-ponding to the position in which the 1 appears.

10
**Octal-to-Binary Encoder**

INPUTS OUTPUTS D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 1 Equations: A2 = D4 + D5 + D6 + D7 A1 = D2 + D3 + D6 + D7 A0 = D1 + D3 + D5 + D7 What type of gates do we need for this encoder? 4-input OR gates

11
Selecting Selecting of data or information is a critical function in digital systems and computers Circuits that perform selecting have: A set of information inputs from which the selection is made A single output A set of control lines for making the selection Logic circuits that perform selecting are called ___________? Selecting can also be done by three-state logic or transmission gates multiplexers

12
Multiplexers A multiplexer selects information from an input line and directs the information to an output line For an n selection inputs (Sn - 1, … S0) called selection inputs, 2n information inputs (I2n - 1, … I0), and one output Y are needed.

13
**2-to-1-Line Multiplexer**

Since 2 information inputs = 21 n = 1 The single selection variable S has two values: S = 0 selects input I0 S = 1 selects input I1 The Output: Y = I0 + SI1 The circuit: S S I 1 Decoder Enabling gates Y

14
**4-to-1-Line Multiplexer**

In general, for an 2n-to-1-line multiplexer: n-to-2n-line decoder 2n x 2 AND-OR S 1 Decoder Y I 2 3

15
**Alternative Function Implementation**

Alternative implementation techniques: Decoders and OR gates Multiplexers (and inverter) ROMs PLAs PALs Can be referred to as structured implementation methods since a specific underlying structure is assumed in each case

16
**Decoders and OR gates - Example**

17
**Decoders and OR gates (continued)**

18
Multiplexer Approach Implement any m functions of n + 1 variables by using: An m-wide 2n-to-1-line multiplexer A single inverter Design: Find the truth table for the functions. Based on the values of the first n variables, separate the truth table rows into pairs For each pair and output, define a basic function of the final variable (0, 1, X,...) Using the first n variables as the index, value-fix the information inputs to the multiplexer with the corresponding rudimentary functions Use the inverter to generate the basic function X

19
**Example: Gray to Binary Code**

Design a circuit to convert a 3-bit Gray code to a binary code The formulation gives the truth table on the right It is obvious from this table that X = C and the Y and Z are more complex Gray A B C Binary x y z 1 0 0 1 1 0 1 0 1 0 1

20
**Gray to Binary (continued)**

Rearrange the table so that the input combinations are in counting order, pair rows, and find the simple functions. Gray A B C Binary x y z Functions of C for y Functions of C for z 0 0 0 0 0 1 1 1 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 F = C F = C F = C F = C F = C F = C F = C F = C

21
**Gray to Binary (continued)**

Assign the variables and functions to the multiplexer inputs: S1 S0 A B D03 D02 D01 D00 Out Y 8-to-1 MUX C Z

22
**Implementing a 4-input Function with a Multiplexer**

23
Read Only Memory Read Only Memories (ROM) or Programmable Read Only Memories (PROM) have: N input lines, M output lines, and 2N decoded minterms. Fixed AND array Programmable OR Array A program for a ROM or PROM is simply a multiple-output truth table If a 1 entry, a connection is made to the corresponding minterm for the corresponding output If a 0, no connection is made

24
**Read Only Memory Example**

Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines) The fixed "AND" array is a “decoder” with 3 inputs and 8 outputs implementing minterms. The programmable "OR“ array uses a single line to represent all inputs to an OR gate. An “X” in the array corresponds to attaching the minterm to the OR Read Example: For input (A2,A1,A0) = 111, output is (F3,F2,F1,F0 ) =_______. D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 A B C F0 F1 F2 F3 X

25
**Programmable Logic - Advantages**

Many programmable logic devices are field- programmable, i. e., can be programmed outside of the manufacturing environment Most programmable logic devices are erasable and reprogrammable. Allows “updating” a device or correction of errors Allows reuse the device for a different design - the ultimate in re-usability! Programmable logic devices can be used to prototype design that will be implemented for sale in regular ICs. Complete Intel Pentium designs were actually prototype with specialized systems based on large numbers of VLSI programmable devices!

26
**Programmable Configurations**

Fixed Programmable Inputs Programmable AND array Outputs Connections OR array (decoder) (a) Programmable read-only memory (PROM) Inputs Programmable Programmable Fixed Outputs Connections AND array OR array (b) Programmable array logic (PAL) device Inputs Programmable Programmable Programmable Programmable Outputs Connections AND array Connections OR array (c) Programmable logic array (PLA) device

27
**Programmable Array Logic Example**

AND gates inputs Product A A B B C C D D W W term 1 X 2 X W 3 X A 4 X 5 X F1 6 X B 7 X 8 X F2 9 X C 10 11 12 D A A B B C C D D W W

28
**Programmable Logic Array Example**

Fuse intact Fuse blown 1 F 2 X A B C 3 4 A B A C B C What are the equations for F1 and F2? 3-input, 3-output PLA with 4 product terms

Similar presentations

© 2021 SlidePlayer.com Inc.

All rights reserved.

To make this website work, we log user data and share it with processors. To use this website, you must agree to our Privacy Policy, including cookie policy.

Ads by Google