CMOS Logic Gates. NMOS transistor acts as a switch 2 When gate voltage is 0 V No channel is formed current does not flow easily “open switch” When gate.

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Presentation transcript:

CMOS Logic Gates

NMOS transistor acts as a switch 2 When gate voltage is 0 V No channel is formed current does not flow easily “open switch” When gate voltage is above threshold voltage electrons are drawn into channel current can flow through channel with little resistance “closed switch” MOS transistors can be used as a voltage-controlled switch This is the basis of computing with 1’s and 0’s!

Simplified Transistor Model Simple model for transistors in CMOS circuits, when V IN is fully logic 0 or logic 1: D G S V GS = 0 V V GS = 5V (for NMOS) V GS = -5V (for PMOS) D G S Transistor is cutoff. Zero current flow. Transistor is not cutoff, but zero current flow of partner transistor causes V DS = 0 V.

Logic Gates We may cleverly position the transistors so that when a combination of high and low voltages is applied at the input, an output voltage appears according to a useful logic function. We call such a circuit a logic gate. We express the operation of the logic gate using a truth table that shows the output (high or low) for each possible combination of high and low input voltages. 4

Inverter (NOT Gate) 5 D S V DD D S V OUT V IN Functional Representation (Symbol) Physical Representation (CMOS circuit) How much detail do you need to show for your application?

Inverter (NOT Gate) 6 Functional Representation (Symbol) A NOT A A Truth Table ANOT A

Verify CMOS Inverter (use switch model) D S 5 V D S V OUT V IN 7 0 V

Verify CMOS Inverter (use switch model) D S 5 V D S V OUT V IN 8 5 V

AND Gate 9 Functional Representation (Symbol) A B A AND B A·B Truth Table A B A AND B

NAND Gate 10 Functional Representation (Symbol) A B A NAND B A·B Truth Table A B A NAND B

CMOS NAND 5V A B S SS S AB

More Practice Verify the logical operation of the CMOS NAND: A = 0V B = 0V A = 0V B = 5V 5V S SS S S SS S

More Practice Verify the logical operation of the CMOS NAND: A = 5V B = 0V A = 5V B = 5V 5V S SS S S SS S

OR Gate 14 Functional Representation (Symbol) A B A OR B A+B Truth Table A B A OR B

NOR Gate 15 Functional Representation (Symbol) A B A NOR B A+B Truth Table A NOR B A B

More Practice Verify the logical operation of the CMOS NOR: A = 0V B = 0V A = 0V B = 5V SS S S 5V SS S S

More Practice Verify the logical operation of the CMOS NOR: A = 5V B = 0V A = 5V B = 5V SS S S 5V SS S S

CMOS Networks Notice that V OUT gets connected to either V DD or ground by “active” (not cutoff) transistors. We say that these active transistors are “pulling up” or “pulling down” the output. NMOS transistors = pull-down network PMOS transistors = pull-up network These networks had better be complementary or V OUT could be “floating”—or attached to both V DD and ground at the same time.

CMOS NAND vs. NOR CMOS NAND 5V S SS S SS S S CMOS NOR

XOR and XNOR Gates 20 A B A XOR B A ⃝ B A XOR B A B A B A XNOR B A ⃝ B A XNOR B A B + +